Transcend SO-DIMM TS128MSD64V3A-I 用户手册
产品代码
TS128MSD64V3A-I
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8
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200PIN DDR333 Unbuffered SO-DIMM
1GB With 64Mx8 CL2.5
Transcend Information Inc.
1
Description
The TS128MSD64V3A-I is a 128M x 64bits Double Data
Rate SDRAM high-density for DDR333. The
TS128MSD64V3A-I consists of 16pcs CMOS 64Mx8 bits
Double Data Rate SDRAMs in 60 Ball FBGA packages and
a 2048 bits serial EEPROM on a 200-pin printed circuit
board. The TS128MSD64V3A-I is a Dual In-Line Memory
Module and is intended for mounting into 200-pin edge
connector sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be useful
for a variety of high bandwidth, high performance memory
system applications.
Features
• Industrial Temperature (TA): -40C to +85C
• RoHS compliant products.
• Power supply: VDD= VDDQ: 2.5V ± 0.1V,
• Max clock Freq: 166MHZ.
• Double-data-rate architecture; two data transfers per
• RoHS compliant products.
• Power supply: VDD= VDDQ: 2.5V ± 0.1V,
• Max clock Freq: 166MHZ.
• Double-data-rate architecture; two data transfers per
clock cycle
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CLK transition
• Commands entered on each positive CLK edge
• Auto and Self Refresh.
• Data I/O transactions on both edge of data strobe.
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
• DLL aligns DQ and DQS transitions with CLK transition
• Commands entered on each positive CLK edge
• Auto and Self Refresh.
• Data I/O transactions on both edge of data strobe.
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
CAS Latency (Access from column address) : 2.5
Burst Length (2,4,8)
Data Sequence (Sequential & Interleave)
Placement
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PCB: 09-1870