Intel Mobile Intel Celeron RH80532NC049256 数据表
产品代码
RH80532NC049256
Electrical Specifications
24
Datasheet
NOTES:
1.
1.
Refer to
for signal descriptions and termination requirements.
2.
In processor systems where there is no debug port implemented on the system board, these signals are
used to support a debug port interposer. In systems with the debug port implemented on the system
board, these signals are no connects.
used to support a debug port interposer. In systems with the debug port implemented on the system
board, these signals are no connects.
3.
BPM[2:1]# and PRDY# are AGTL+ output only signals.
4.
PROCHOT# signal type is open drain output and CMOS input.
5.
On die termination differs from other AGTL+ signals.
Table 4.
FSB Pin Groups
Signal Group
Type
Signals
1
AGTL+ Common Clock Input
Synchronous
to BCLK[1:0]
to BCLK[1:0]
BPRI#, DEFER#, PREQ#
5
, RESET#, RS[2:0]#, TRDY#
AGTL+ Common Clock I/O
Synchronous
to BCLK[1:0]
to BCLK[1:0]
ADS#, BNR#, BPM[3:0]#
3
, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, PRDY#
3
, DPWR#
AGTL+ Source Synchronous
I/O
I/O
Synchronous
to assoc.
strobe
to assoc.
strobe
AGTL+ Strobes
Synchronous
to BCLK[1:0]
to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
CMOS Input
Asynchronous
A20M#, DPRSTP#, DPSLP#, IGNNE#, INIT#, LINT0/INTR,
LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
LINT1/NMI, PWRGOOD, SMI#, SLP#, STPCLK#
Open Drain Output
Asynchronous
FERR#, IERR#, THERMTRIP#
Open Drain I/O
Asynchronous
PROCHOT#
4
CMOS Output
Asynchronous
PSI#, VID[6:0], BSEL[2:0]
CMOS Input
Synchronous
to TCK
to TCK
TCK, TDI, TMS, TRST#
Open Drain Output
Synchronous
to TCK
to TCK
TDO
FSB Clock
Clock
BCLK[1:0]
Power/Other
COMP[3:0], DBR#
2
, GTLREF, RSVD, TEST2, TEST1, THERMDA,
THERMDC, V
CC
, V
CCA
, V
CCP,
V
CC_SENSE
, V
SS,
V
SS_SENSE
Signals
Associated Strobe
REQ[4:0]#,
A[16:3]#
ADSTB[0]#
A[35:17]#
ADSTB[1]#
D[15:0]#,
DINV0#
DINV0#
DSTBP0#,
DSTBN0#
DSTBN0#
D[31:16]#,
DINV1#
DINV1#
DSTBP1#,
DSTBN1#
DSTBN1#
D[47:32]#,
DINV2#
DINV2#
DSTBP2#,
DSTBN2#
DSTBN2#
D[63:48]#,
DINV3#
DINV3#
DSTBP3#,
DSTBN3#
DSTBN3#