National Instruments NI 5102 用户手册
Index
I-4
ni.com
NI-DAQ driver software
overview of NI-DAQ API, 1-4
relationship with programming
relationship with programming
environment and hardware (figure), 1-3
NI Developer Zone, B-1
NI-SCOPE driver, 1-4
Nyquist theorem, 3-1
NI-SCOPE driver, 1-4
Nyquist theorem, 3-1
O
optional equipment, 1-6
P
passive probe, 3-8 to 3-11
compensating the probe, 3-9 to 3-11
connecting probe compensation
cabling (figure), 3-10
probe compensation comparison
(figure), 3-11
typical X10 probe (figure), 3-8
peak-to-peak value
description, 3-5
dynamic range of 8-bit ADC (figure), 3-6
dynamic range of 8-bit ADC (figure), 3-6
PFI lines, 4-20 to 4-21
digital trigger specifications, A-4 to A-5
input lines, 4-20
output lines, 4-20 to 4-21
input lines, 4-20
output lines, 4-20 to 4-21
PFI1 signal (table), 4-5
PFI2 signal (table), 4-5
physical specifications, A-5
Plug and Play compliance, 1-1
posttrigger acquisition, 4-8 to 4-10
PFI2 signal (table), 4-5
physical specifications, A-5
Plug and Play compliance, 1-1
posttrigger acquisition, 4-8 to 4-10
acquisition signals (table), 4-10
possible number of samples (table), 4-9
timing signals (figure), 4-9
trigger hold-off (figure), 4-16
possible number of samples (table), 4-9
timing signals (figure), 4-9
trigger hold-off (figure), 4-16
power consumption specifications, A-5
pretrigger acquisition, 4-11 to 4-13
pretrigger acquisition, 4-11 to 4-13
acquisition signals (table), 4-13
possible number of samples (table), 4-11
possible number of samples (table), 4-11
timing signals (figure), 4-12
trigger hold-off (figure), 4-16
trigger hold-off (figure), 4-16
probes and waveform effect, 3-8 to 3-11
active and current probes, 3-11
compensating the probe, 3-9 to 3-11
passive probe, 3-8 to 3-11
compensating the probe, 3-9 to 3-11
passive probe, 3-8 to 3-11
PXI-compatible products
NI 5102 J2 pin assignments (table), 1-6
using with standard CompactPCI,
using with standard CompactPCI,
1-5 to 1-6
R
random interleaved sampling (RIS), 4-17
record length, 3-4 to 3-5
requirements for getting started, 2-1 to 2-2
RIS (random interleaved sampling), 4-17
RTSI bus clock line
record length, 3-4 to 3-5
requirements for getting started, 2-1 to 2-2
RIS (random interleaved sampling), 4-17
RTSI bus clock line
overview, 4-19
specifications, A-5
specifications, A-5
RTSI bus trigger lines, 4-18 to 4-19
illustration, 4-19
NI 5102 (PCI and ISA), 4-18 to 4-19
NI 5102 (PXI), 4-19
specifications, A-5
NI 5102 (PCI and ISA), 4-18 to 4-19
NI 5102 (PXI), 4-19
specifications, A-5
S
safety specifications, A-6
sample rate, 3-3
sample rate, 3-3
1MHz sine wave (figure), 3-3
definition, 3-3
definition, 3-3
Scan Clock signal
ADC pipeline delay, 4-8
Scan Clock delay (figure), 4-8
PFI output, 4-20
posttrigger acquisition (table), 4-10
pretrigger acquisition (table), 4-13
trigger source (figure), 4-14
posttrigger acquisition (table), 4-10
pretrigger acquisition (table), 4-13
trigger source (figure), 4-14
Scan Counter Terminal Count signal
(table), 4-13