Intel netstructure mpcbl0001 用户手册
Technical Product Specification
139
Order #273817
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Contents
2. Clear CMOS Jumper enabled
3. MFG Jumper installed.
9.2
Port 80h POST Codes
During the POST, the BIOS generates diagnostic progress codes (POST-codes) to I/O port 80h. If
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
the POST fails, execution stops and the last POST code generated is left at port 80h. This code is
useful for determining the point where an error occurred.
Displaying the POST codes requires an add-in card, often called a POST card (PCI, not ISA). The
POST card decodes the port and displays the contents on a medium such as a seven-segment
display.
POST card decodes the port and displays the contents on a medium such as a seven-segment
display.
, and
offer descriptions of the POST codes generated by the BIOS.
They define the uncompressed INIT code checkpoints, the boot block recovery code checkpoints,
and the runtime code uncompressed in F000 shadow RAM.
and the runtime code uncompressed in F000 shadow RAM.
Note:
Some codes are repeated in the tables because they apply to more than one operation.
Table 90.
Bootblock Initialization Code Checkpoints
Checkpoint
Description
Before D1
Early chipset initialization is done. Early super I/O initialization is done, including RTC and
keyboard controller. NMI is disabled.
keyboard controller. NMI is disabled.
D1
Perform keyboard controller BAT test. Check if waking up from power management suspend
state. Save power-on CPUID value in scratch CMOS.
state. Save power-on CPUID value in scratch CMOS.
D0
Go to flat mode with 4 GByte limit and GA20 enabled. Verify the bootblock checksum.
D2
Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat
mode is enabled.
mode is enabled.
D3
If memory sizing module not executed, start memory refresh and do memory sizing in
Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode
is enabled.
Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode
is enabled.
D4
Test base 512 KByte memory. Adjust policies and cache first 8 GBytes. Set stack.
D5
Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS
now executes out of RAM.
now executes out of RAM.
D6
Both key sequence and OEM-specific methods are checked to determine if BIOS recovery is
forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to
checkpoint E0.
forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to
checkpoint E0.
D7
Restore CPUID value back into register. The Bootblock-Runtime interface module is moved
to system memory and control is given to it. Determine whether to execute serial flash.
to system memory and control is given to it. Determine whether to execute serial flash.
D8
The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9
Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory.
Leaves all RAM below 1 MByte Read-Write including E000 and F000 shadow areas but
closing SMRAM.
Leaves all RAM below 1 MByte Read-Write including E000 and F000 shadow areas but
closing SMRAM.
DA
Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel).
See
See
for more information.
E1-E8
EC-EE
EC-EE
OEM memory detection/configuration error. This range is reserved for chipset vendors and
system manufacturers. The error associated with this value may different from one platform
to the next.
system manufacturers. The error associated with this value may different from one platform
to the next.