Intel X5675 AT80614006696AA 用户手册
产品代码
AT80614006696AA
Signal Definitions
112
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
DBR#
I
DBR# is used only in systems where no debug port is implemented on the
system board. DBR# is used by a debug port interposer so that an in-target
probe can drive system reset.
DDR_COMP[2:0]
I
Must be terminated on the system board using precision resistors.
DDR_THERM#
I
DDR_THERM# is used for imposing duty cycle throttling on all memory
channels. The platform should ensure that DDR_THERM# is asserted when any
DIMM is over T64.
DDR_THERM2#
I
DDR_THERM2# is used for imposing duty cycle throttling on all memory
channels or implementing 2X Refresh.
DDR{0/1/2}_BA[2:0]
O
Defines the bank which is the destination for the current Activate, Read, Write,
or Precharge command.
1
DDR{0/1/2}_CAS#
O
Column Address Strobe.
DDR{0/1/2}_CKE[3:0]
O
Clock Enable.
DDR{0/1/2}_CLK_N[3:0]
DDR{0/1/2}_CLK_P[3:0]
DDR{0/1/2}_CLK_P[3:0]
O
Differential clocks to the DIMM. All command and control signals are valid on
the rising edge of clock.
DDR{0/1/2}_CS[7:0]#
O
Each signal selects one rank as the target of the command and address.
DDR{0/1/2}_DQ[63:0]
I/O
DDR3 Data bits.
DDR{0/1/2}_DQS_N[17:0]
DDR{0/1/2}_DQS_P[17:0]
DDR{0/1/2}_DQS_P[17:0]
I/O
Differential pair, Data/ECC Strobe. Differential strobes latch data/ECC for each
DRAM. Different numbers of strobes are used depending on whether the
connected DRAMs are x4,x8. Driven with edges in center of data, receive edges
are aligned with data edges.
DDR{0/1/2}_ECC[7:0]
I/O
Check Bits - An Error Correction Code is driven along with data on these lines
for DIMMs that support that capability.
DDR{0/1/2}_MA[15:0]
O
Selects the Row address for Reads and writes, and the column address for
activates. Also used to set values for DRAM configuration registers.
DDR{0/1/2}_MA_PAR
O
Odd parity across Address and Command.
DDR{0/1/2}_ODT[3:0]
O
Enables various combinations of termination resistance in the target and non-
target DIMMs when data is read or written
DDR{0/1/2}_PAR_ERR#[2:
0]
I
Parity Error detected by Registered DIMM (one for each DIMM).
DDR{0/1/2}_RAS#
O
Row Address Strobe.
DDR{0/1/2}_RESET#
O
Resets DRAMs. Held low on power up, held high during self refresh, otherwise
controlled by configuration register.
DDR_VREF
I
Voltage reference for DDR3.
DDR{0/1/2}_WE#
O
Write Enable.
GTLREF
I
Voltage reference for GTL signals.
ISENSE
I
Analog input voltage with respect to VSS for sensing core current consumption,
comes from VR11.1.
PECI
I/O
PECI (Platform Environment Control Interface) is the serial sideband interface
to the processor and is used primarily for thermal, power and error
management.
PECI_ID#
I
PECI_ID# is the PECI client address identifier. This pin is active low and
asserted when tied to VSS. Assertion of this pin results in a PECI client address
of 0x31 (versus the default 0x30 client address). This pin is primarily useful for
PECI client address differentiation in DP platforms and must be pulled up to
VTT on one socket and down to VSS on the other.
PRDY#
O
PRDY# is a processor output used by debug tools to determine processor
debug readiness.
PREQ#
I/O
PREQ# is used by debug tools to request debug operation of the processor.
Table 6-1.
Signal Definitions (Sheet 2 of 4)
Name
Type
Description
Notes