Intel 2760QM FF8062701065300 用户手册
产品代码
FF8062701065300
Datasheet, Volume 1
59
Electrical Specifications
Notes:
1.
1.
Refer to
Table 7-16
for details on the R
ON
(Buffer on Resistance) value for this signal.
7.3
Power-On Configuration (POC) Options
Several configuration options can be configured by hardware. The processor samples
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to
its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or
upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these
options, refer to
Table 7-7
.
The sampled information configures the processor for subsequent operation. These
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
configuration options cannot be changed except by another reset transition of the
latching signal (RESET_N or PWRGOOD).
Notes:
1.
1.
BIST_ENABLE is sampled at RESET_N de-assertion.
2.
This signal is sampled at PWRGOOD assertion.
Power/Other Signals
Power / Ground
VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA
and VSS
and VSS
Sense Points
VCC_SENSE
VSS_VCC_SENSE
VSS_VTTD_SENSE
VTTD_SENSE
VSA_SENSE
VSS_VSA_SENSE
VSS_VCC_SENSE
VSS_VTTD_SENSE
VTTD_SENSE
VSA_SENSE
VSS_VSA_SENSE
Notes:
1.
Refer to
Chapter 6, "Signal Descriptions,"
for signal description details.
2.
DDR{0/1/2/3} refers to DDR3 Channel 0, DDR3 Channel 1, DDR3 Channel 2, and DDR3 Channel 3.
3.
ECC DIMMs are not supported on the processor; thus, these signals are not used.
Table 7-6.
Signals with On-Die Termination
Signal Name
Pull Up /Pull
Down
Rail
Value
Units
Notes
BCLK_SELECT[1:0]
Pull up
VTT
2K
Ohm
BIST_ENABLE
Pull Up
VTT
2K
Ohm
EAR_N
Pull Up
VTT
2K
Ohm
1
Table 7-5.
Signal Groups (Sheet 3 of 3)
Differential/Single
Ended
Buffer Type
Signals
1
Table 7-7.
Power-On Configuration Option Lands
Configuration Option
Land Name
Notes
BCLK input select
BCLK_SELECT[1:0]
Execute BIST (Built-In Self Test)
BIST_ENABLE
1
Power-up Sequence Halt for ITP configuration
EAR_N
2