Shanghai SIMCom Wireless Solutions Limited 8PSA301 用户手册
Smart Machine Smart Decision
28
ESD component and bypass caps should be placed closed to USIM Card
USIM card signals should be far away from other high-speed signal
USIM card signals should be far away from other high-speed signal
MIPI_DSI/CSI
Protect MIPI_DSI/CSI signals from noisy signals (clocks, SMPS, etc.)
Differential pairs, 100 Ω nominal, ±10%
Total routing length < 305 mm
Intra-pair length matching < 5 ps (0.67 mm)
Inter-pair length matching < 10 ps (1.3 mm)
Lane-to-lane trace spacing = 3x line width
Spacing to all other signals = 4x line width
Maintain a solid ground reference for clocks to provide a low-impedance path for return currents
Each trace needs to be next to a ground plane
Minimize the number of via on the trace
Intra-pair length matching < 5 ps (0.67 mm)
Inter-pair length matching < 10 ps (1.3 mm)
Lane-to-lane trace spacing = 3x line width
Spacing to all other signals = 4x line width
Maintain a solid ground reference for clocks to provide a low-impedance path for return currents
Each trace needs to be next to a ground plane
Minimize the number of via on the trace
Refer to the following table for the length of MIPI traces inside the module.
Table 16: Length of MIPI traces inside the module
Pin#
Net Name
Length(mm)
52
MIPI_DSI_CLK_M
8.08
53
MIPI_DSI_CLK_P
9.03
54
MIPI_DSI_LANE0M
9.04
55
MIPI_DSI_LANE0P
8.73
56
MIPI_DSI_LANE1M
9.29
57
MIPI_DSI_LANE1P
9.10
58
MIPI_DSI_LANE2M
8.69
59
MIPI_DSI_LANE2P
8.95
60
MIPI_DSI_LANE3M
9.10
61
MIPI_DSI_LANE3P
9.85
63
MIPI_CSI0_CLK_M
14.04
64
MIPI_CSI0_CLK_P
13.79
65
MIPI_CSI0_LN0_M
13.27
66
MIPI_CSI0_LN0_P
13.23
67
MIPI_CSI0_LN1_M
13.96
68
MIPI_CSI0_LN1_P
14.49
70
MIPI_CSI1_CLK_M
17.21
71
MIPI_CSI1_CLK_P
17.69
72
MIPI_CSI1_LN0_M
16.34
73
MIPI_CSI1_LN0_P
17.25
USB
90 Ω differential, ± 10% trace impedance
Differential data pair matching < 6.6 mm (50 ps)