Transcend 1GB DDR2 DDR2-533 Unbuffer Non-ECC Memory TS128MLQ64V5J 用户手册
产品代码
TS128MLQ64V5J
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240PIN DDR2 533 Unbuffered DIMM
1GB With 64Mx8 CL4
Transcend Information Inc.
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Description
Placement
The TS128MLQ64V5J is a 128M x 64bits DDR2-533
Unbuffered DIMM. The TS128MLQ64V5J consists of
16pcs 64Mx8bits DDR2 SDRAMs in 60 ball FBGA
packages and a 2048 bits serial EEPROM on a 240-pin
printed circuit board. The TS128MLQ64V5J is a Dual
In-Line Memory Module and is intended for mounting into
240-pin edge connector sockets.
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Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• RoHS compliant products.
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 267MHZ; 533Mb/S/Pin.
• Posted CAS
• Programmable CAS Latency: 3,4,5
• Programmable Additive Latency :0, 1,2,3 and 4
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4,8(Interleave/nibble sequential)
• JEDEC standard 1.8V ± 0.1V Power supply
• VDDQ=1.8V ± 0.1V
• Max clock Freq: 267MHZ; 533Mb/S/Pin.
• Posted CAS
• Programmable CAS Latency: 3,4,5
• Programmable Additive Latency :0, 1,2,3 and 4
• Write Latency (WL) = Read Latency (RL)-1
• Burst Length: 4,8(Interleave/nibble sequential)
• Programmable sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended
PCB: 09-2345
data-strobe is an optional feature)
• Off-Chip Driver (OCD) Impedance Adjustment
• MRS cycle with address key programs.
• On Die Termination
• Refresh and Self Refresh
• MRS cycle with address key programs.
• On Die Termination
• Refresh and Self Refresh
Average Refresh Period 7.8us at lower then TCASE
85°C, 3.9us at 85°C < TCASE < 95 °C
• Serial presence detect with EEPROM