Intel P4500 CP80617004803AA 数据表
产品代码
CP80617004803AA
Interfaces
32
Datasheet
2.4.2
Integrated Graphics Display Pipes
The integrated graphics controller display pipe can be broken down into three
components:
components:
Display Planes
Display Pipes
Embedded DisplayPort and Intel FDI
2.4.2.1
Display Planes
A display plane is a single displayed surface in memory and contains one image
(desktop, cursor, overlay). It is the portion of the display HW logic that defines the
format and location of a rectangular region of memory that can be displayed on display
output device and delivers that data to a display pipe. This is clocked by the Core
Display Clock.
(desktop, cursor, overlay). It is the portion of the display HW logic that defines the
format and location of a rectangular region of memory that can be displayed on display
output device and delivers that data to a display pipe. This is clocked by the Core
Display Clock.
2.4.2.1.1
Planes A and B
Planes A and B are the main display planes and are associated with Pipes A and B
respectively. The two display pipes are independent, allowing for support of two
independent display streams. They are both double-buffered, which minimizes latency
and improves visual quality.
respectively. The two display pipes are independent, allowing for support of two
independent display streams. They are both double-buffered, which minimizes latency
and improves visual quality.
2.4.2.1.2
Sprite A and B
Sprite A and Sprite B are planes optimized for video decode, and are associated with
Planes A and B respectively. Sprite A and B are also double-buffered.
Planes A and B respectively. Sprite A and B are also double-buffered.
Figure 2-8. Processor Display Block Diagram
Plane A
Cursor B
Sprite B
Plane B
Cursor A
Sprite A
Pipe B
Pipe A
Alpha
Blend/
Gamma/
Panel
Fitter
Fitter
M
U
X
X
eDP
Intel®
FDI
VGA