Intel P4500 CP80617004803AA 数据表
产品代码
CP80617004803AA
Datasheet
91
Electrical Specifications
7.6
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in
Table 7-37
.
The buffer type indicates which signaling technology and specifications apply to the
signals. All the differential signals, and selected DDR3 and Control Sideband signals
have On-Die Termination (ODT) resistors. There are some signals that do not have ODT
and need to be terminated on the board.
signals. All the differential signals, and selected DDR3 and Control Sideband signals
have On-Die Termination (ODT) resistors. There are some signals that do not have ODT
and need to be terminated on the board.
Table 7-37.Signal Groups
1
(Sheet 1 of 3)
Signal Group
Alpha
Group
Type
Signals
System Reference Clock
Differential
(a)
CMOS Input
BCLK, BCLK#
PEG_CLK, PEG_CLK#
DPLL_REF_SSCLK, DPLL_REF_SSCLK#
Differential
(b)
CMOS Output
BCLK_ITP, BCLK_ITP#
DDR3 Reference Clocks
2
Differential
(c)
DDR3 Output
SA_CK[1:0], SA_CK#[1:0]
SB_CK[1:0], SB_CK#[1:0]
DDR3 Command Signals
2
Single Ended
(d)
DDR3 Output
SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#
SA_WE#, SB_WE#
SA_MA[15:0], SB_MA[15:0]
SA_BS[2:0], SB_BS[2:0]
SA_DM[7:0], SB_DM[7:0]
SM_DRAMRST#
SA_CS#[1:0], SB_CS#[1:0]
SA_ODT[1:0], SB_ODT[1:0]
SA_CKE[1:0], SB_CKE[1:0]
DDR3 Data Signals
2
Single ended
(e)
DDR3 Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
Differential
(f)
DDR3 Bi-directional
SA_DQS[7:0], SA_DQS#[7:0]
SB_DQS[7:0], SB_DQS#[7:0]
TAP (ITP/XDP)
Single Ended
(g)
CMOS Input
TCK, TMS, TRST#
Single Ended
(ga)
CMOS Input
TDI,TDI_M
Single Ended
(h)
CMOS Open-Drain
Output
Output
TDO, TDO_M
Single Ended
(i)
Asynchronous
CMOS Output
CMOS Output
TAPPWRGOOD