Transcend 1GB DDR333 Unbuffer Non-ECC Memory TS128MLD64V3J 用户手册

 

 

Transcend Information Inc.

 

1

Description 

The TS128MLD64V3J is a 64Mx64bits Double Data Rate 

SDRAM high-density Module for DDR333. The 

TS128MLD64V3J consists of 16pcs CMOS 64Mx8 bits 

Double Data Rate SDRAMs in 66 pin TSOP-II 400mil 

packages and a 2048 bits serial EEPROM on a 184-pin 

printed circuit board. The TS128MLD64V3J is a Dual 

In-Line Memory Module and is intended for mounting into 

184-pin edge connector sockets. 

Synchronous design allows precise cycle control with the 

use of system clock. Data I/O transactions are possible 

on both edges of DQS. Range of operation frequencies, 

programmable latencies allow the same device to be 

useful for a variety of high bandwidth, high performance 

memory system applications. 

•  Power supply: VDD: 2.5V ± 0.2V, VDDQ: 2.5V ±0.2V 
•  Max clock Freq: 166MHZ. 
•  Double-data-rate architecture; two data transfers per        

clock cycle 

•  Differential clock inputs (CK and /CK) 
•  Burst Mode Operation. 
•  Auto and Self Refresh. 
•  Data I/O transactions on both edge of data strobe. 
•  Edge aligned data output, center aligned data input. 
•  Serial Presence Detect (SPD) with serial EEPROM   
•  SSTL-2 compatible inputs and outputs. 
•  MRS cycle with address key programs. 

CAS Latency (Access from column address): 2.5 

Burst Length (2, 4, 8 ) 

Data Sequence (Sequential & Interleave) 

E

I

A

B

D

H

G

F

C