Intel III Xeon 700 MHz 80526KY7002M 用户手册
产品代码
80526KY7002M
ELECTRICAL SPECIFICATIONS
24
3.12
System Bus AC Specifications
The system bus timings specified in this section are defined at the processor core pins unless otherwise noted. Timings
are tested at the processor core during manufacturing.
NOTE: Timing specifications T45-T49 are reserved for future use.
All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+
timings are referenced to 2/3 VTT for both ‘0’ and ‘1’ logic levels unless otherwise specified.
are tested at the processor core during manufacturing.
NOTE: Timing specifications T45-T49 are reserved for future use.
All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+
timings are referenced to 2/3 VTT for both ‘0’ and ‘1’ logic levels unless otherwise specified.