Intel G2100T CM8063701219000 用户手册
产品代码
CM8063701219000
Processor Configuration Registers
70
Datasheet, Volume 2
2.5.23
LAC—Legacy Access Control Register
This 8-bit register controls steering of MDA cycles and a fixed DRAM hole from 15-
16 MB.
16 MB.
There can only be at most one MDA device in the system.
B/D/F/Type:
0/0/0/PCI
Address Offset:
87h
Reset Value:
00h
Access:
RW
Size:
8 bits
BIOS Optimal Default
0h
Bit
Attr
Reset
Value
RST/
PWR
Description
7
RW
0b
Uncore
Hole Enable (HEN)
This field enables a memory hole in DRAM space. The DRAM that
This field enables a memory hole in DRAM space. The DRAM that
lies "behind" this space is not remapped.
0 = No memory hole.
0 = No memory hole.
1 = Memory hole from 15 MB to 16 MB.
This bit is Intel TXT lockable.
This bit is Intel TXT lockable.
6:4
RO
0h
Reserved
3
RW
0b
Uncore
PEG60 MDA Present (MDAP60)
This bit works with the VGA Enable bits in the BCTRL register of
This bit works with the VGA Enable bits in the BCTRL register of
Device 6 Function 0 to control the routing of processor initiated
transactions targeting MDA compatible I/O and memory address
ranges. This bit should not be set if the device 6 VGA Enable bit is
not set.
If Device 6 Function 0 VGA enable bit is not set, then accesses to
If Device 6 Function 0 VGA enable bit is not set, then accesses to
I/O address range x3BCh–x3BFh remain on the backbone.
If the VGA enable bit is set and MDA is not present, then accesses
If the VGA enable bit is set and MDA is not present, then accesses
to I/O address range x3BCh–x3BFh are forwarded to PCI Express
through Device 6 Function 0, if the address is within the
corresponding IOBASE and IOLIMIT; otherwise, they remain on the
backbone.
MDA resources are defined as the following:
MDA resources are defined as the following:
Memory:0B0000h–0B7FFFh
I/O:
I/O:
3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh,
(including ISA address aliases, A[15:10] are not used
in decode)
Any I/O reference that includes the I/O locations listed above, or
their aliases, will remain on the backbone even if the reference also
includes I/O locations not listed above.
The following table shows the behavior for all combinations of MDA
The following table shows the behavior for all combinations of MDA
and VGA:
VGAEN
VGAEN
MDAP Description
0
0
All References to MDA and VGA space are not
claimed by Device 6 Function 0.
0
1
Illegal combination
1
0
All VGA and MDA references are routed to PCI
Express Graphics Attach Device 6 Function 0.
1
1
All VGA references are routed to PCI Express
Graphics Attach Device 6 Function 0. MDA
references are not claimed by Device 6 Function
0.
VGA and MDA memory cycles can only be routed across PEG60
when MAE (PCICMD60[1]) is set. VGA and MDA I/O cycles can only
be routed across PEG60 if IOAE (PCICMD60[0]) is set.
Encoding:
0 = No MDA
Encoding:
0 = No MDA
1 = MDA Present