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8
3.6.1 PWR_OK
The power supply accepts a logic collector level which will disable/enable
all the output voltages. As the logic level is low, output voltages are enable;
As the logic level is high, output voltages are disable. The definition of
logic low/high level is as:
High Level: 2.50V ~ 5.25V while sourcing 0.4mA maximum
Low Level: 0.0V ~ 0.50V while sinking 5.0mA maximum
Rise Time: 3.0ms maximum (10.0% ~ 90.0%)
3.6.2 PS_ON# Signal
The power supply provides an internal pull-up to TTL high. The power supply also
provides debounce circuitry on PS_ON# to prevent it from oscillating on/off at startup
when activated by a mechanical switch. The DC output enable circuitry is
SELV-complaint.
Min.
Max.
V
IL
, Input Low Voltage
0.0V
0.8V
V
IL
, Input Low Current (Vin = 0.4 V)
-1.6mA
V
IH
, Input High Voltage (lin = -200 μA)
2.0V
V
IH
, open circuit, lin = 0
5.25V
Table 8. PS_ON# Signal Characteristics
3.6.3 +5VSB
The +5VSB is capable of delivering a maximum of 2.5A at
+5V ±5% to external circuit. The power supply +5VSB is with
over current protection.
3.6.4 5vsb Power-on Time
. The +5VSB has a power-on time of two seconds maximum after application of
valid AC
voltages. (Figure 1)
3.6.5 Output Rise time
The output voltages rise from
10% of nominal to within the regulation ranges within
0.1ms to 20ms (
0.1ms
T2 20ms). (Figure 1)
3.6.6 Overshoot at Turn-on / Turn-off
Any overshoot at turn on or turn off is under 10% of the nominal DC
output voltage with further stipulation that all DC outputs are within their
specified DC voltage ranges before the generation of the power good
signal. Additionally, no voltage may undershoot or overshoot once the