Intermec 073290-001 用户手册

•  SPEED/RANGE/GOODREAD is set high or low depending on the 

scanner. This is a general-purpose control line used for spotter beam 
control, scan speed selection, GoodRead indication on tethered scanner, 
or serial TxD to decoded-output scanners, depending on the installed 
scanner (See “Using the Scanner Interface Signal Set” on page 76). 

Normally, these signals are all driven at 3.3V levels. But signals 
SCAN_FLASH_EN*, ILLUM_LASEN_RTS, and 
SPEED/RANGE/GOODREAD can be redefined in the FPGA as 5V-
tolerant open-drain outputs. This is required for the 5V SE1200 scan 
engines, which otherwise would interpret a 3.3V level as low. It is also 
used for some tethered scanners, like the 1550C. 

While scanning, DBP and SOS signals from the scanner are buffered by 
Schmitt-trigger U9 and routed to count gathering logic in the FPGA. A 
16-bit counter measures the time between DBP edges (bars and spaces) to 
create video “counts” that are collected in a 32-deep FIFO, which in turn 
feeds a 16-deep 32-bit-wide DMA buffer. When the DMA buffer is half 
full, the FPGA asserts SCAN_DREQ to the PXA255 to request a DMA 
transfer, and eight 32-bit words are direct memory accessed into a cached 
area of system SDRAM for decoding. SOS transitions generate interrupts 
to the PXA255 to signal start and end of a frame of data.   

At the end of a frame, FPGA logic appends a 0xFFFF end-of-data marker 
to the accumulated data and then pads the data with a DBP polarity value 
until the DMA buffer contains a complete DMA record. The DBP 
polarity value is 0xFFFA if DBP_HSYNC was high the last count 
recorded, 0xFFF5 if it was low. 

See 605879, Existing Interface Specification, for more detail on this 
scanner interface protocol. 

Wands and wand-emulation devices also use the count gathering logic 
described in “1D DBP Scanner Interface” on page 78, except that only the 
DBP_HSYNC signal is used. Since there are no SOS or TRIGGER signals 
from the input device, the FPGA is configured by software to 
automatically start its count gathering logic on the first DBP_HSYNC 
transition, which is either the wand paper-detect or the first bar of a label. 
In the absence of SOS strobes, counter overflow is used to sense the end of 
scanned data and append the end-of-data and polarity markers. 

Internal 2D imagers are handled through custom interface logic in the 
FPGA.