Intermec 073293-001 用户手册
Chapter 4 — Theory of Operation
The module is interfaced through a 4-wire serial connection to the
PXA255’s “BT” UART. This UART, and its counterpart in the Bluetooth
module, are capable of high-speed operation (up to 921.6kbps), but in the
current software are run at 115.2kbps. The operating system maps this
port as COM4.
PXA255’s “BT” UART. This UART, and its counterpart in the Bluetooth
module, are capable of high-speed operation (up to 921.6kbps), but in the
current software are run at 115.2kbps. The operating system maps this
port as COM4.
No Bluetooth reset is provided – the Bluetooth module generates its own
Power-on reset. However, capacitor C153 can be installed to provide a
reset when an Alps BC02 module is used. The module’s PCM interface is
not used.
Power-on reset. However, capacitor C153 can be installed to provide a
reset when an Alps BC02 module is used. The module’s PCM interface is
not used.
The Bluetooth module firmware interfaces to the CK30 at the Bluetooth
HCI layer. The higher stack levels are provided by Microsoft’s Bluetooth
driver and are included in the CK30 OS image.
HCI layer. The higher stack levels are provided by Microsoft’s Bluetooth
driver and are included in the CK30 OS image.
Storage Card (SD card)
Sandisk SD (Secure Digital) cards are supported in 1-bit mode through
SD slot J17 and the SD/MMC controller in the PXA255 processor. For
details of the SD interface and protocol, refer to the SD spec, and to
278693-001, Intel® PXA255 Processor Developer’s Manual, Revision -001,
January 2003.
SD slot J17 and the SD/MMC controller in the PXA255 processor. For
details of the SD interface and protocol, refer to the SD spec, and to
278693-001, Intel® PXA255 Processor Developer’s Manual, Revision -001,
January 2003.
The SD card is powered through FET Q10. Software normally turns on
power through control signal SD_PWR_EN* only when an SD card is
detected in the slot while the CK30 is on. Software is responsible for
shutting off SD power in a critical battery situation. If SD power is still on
when the system suspends, it is shut off in hardware by the “Type 2”
interlock mechanism described in “Device Power Control” on page 58.
power through control signal SD_PWR_EN* only when an SD card is
detected in the slot while the CK30 is on. Software is responsible for
shutting off SD power in a critical battery situation. If SD power is still on
when the system suspends, it is shut off in hardware by the “Type 2”
interlock mechanism described in “Device Power Control” on page 58.
The SDMMC_IRQ* signal is provided for future SDIO support, but is
currently not used.
currently not used.
SD card-detect and write-protect status are sensed through mechanical
switches in the slot connector. The SDMMC_CD and SDMMC_WP*
signals are monitored through PXA255 GPIO5 and GPIO32. Resistor
R189 is provided in the ground path for these switches so that the
functional test fixture can override the actual switch settings to simulate
insertion and removal of a card. Note that the mechanical card-detect
switch has been found to be unreliable, and can report the wrong card
state, especially in a drop.
switches in the slot connector. The SDMMC_CD and SDMMC_WP*
signals are monitored through PXA255 GPIO5 and GPIO32. Resistor
R189 is provided in the ground path for these switches so that the
functional test fixture can override the actual switch settings to simulate
insertion and removal of a card. Note that the mechanical card-detect
switch has been found to be unreliable, and can report the wrong card
state, especially in a drop.
In later revisions of the PCB, the card detect switch is not used, and
alternate card detect scheme based on the SD card DAT3 data line
(currently unused in the CK30’s 1-bit interface) is used instead. In this
scheme, the SD card DAT3 is routed directly to PXA255 GPIO5, and is
held low by a weak pull-down (R182). SD slot power is enabled
continuously while the computer is on. An installed SD card pulls DAT3
high through a weak internal pull-up, overpowering R182. A high-going
transition on GPIO5 is interpreted as a card insertion, and a low-going
transition as a card removal.
alternate card detect scheme based on the SD card DAT3 data line
(currently unused in the CK30’s 1-bit interface) is used instead. In this
scheme, the SD card DAT3 is routed directly to PXA255 GPIO5, and is
held low by a weak pull-down (R182). SD slot power is enabled
continuously while the computer is on. An installed SD card pulls DAT3
high through a weak internal pull-up, overpowering R182. A high-going
transition on GPIO5 is interpreted as a card insertion, and a low-going
transition as a card removal.
CK30 Handheld Computer Service Manual
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