Intermec 073294-001 用户手册

The output, BATT_FAULT* then gates off the load enable lines through 
gates U17, U25, and U26. Flip-flop U15 latches the state of 
BATT_FAULT* so that these loads do not come back on again when 
power is restored. 

OK 

Not important 

Controlled by software 

Critical or battery out 

Awake 

Controlled by software 

Critical or battery out 

Suspended 

Off 

PIC processor U38 (the PSC, or Power Supply Controller) is used to 
supervise the following low-level power management functions. These are 
discussed in further detail later in this section. 

• Reset control 

•  IO key suspend/resume control 

•  Battery voltage A/D 

• Temperature A/D 

•  Suspend timeout “enforcement” 

• Supercap charging 

•  Battery status LED control 

•  FPGA IO power control 

The microcontroller is flash-based and can be reprogrammed in-system 
through the Debug port (P1) behind the SD slot door (see “PSC PIC” on 
page 96). While the CK30 is on, the PSC functions as a peripheral of the 
power management code running on the PXA255, accepting commands 
and returning data over the I2C bus. 

The I2C controller in the PXA255 is always the host; the PSC is always a 
slave device at address 0x12. The following I2C bus protocol is used to 
send commands to the PSC and read data back.  All commands to the 
PSC are 1 byte long. The PSC echoes back the command byte, followed 
by a single data byte. 

Host sends: 

[Start] [Slave ADDR write]

[ack]

 [CMD1]

[ack]

 ([CMD2]

[ack]

…[CMDn]

[ack]

) 

[Start] [Slave ADDR read]

[ack] 

Where 

[ack]

 

= ACK

 

from PSC 

PSC responds: 

[CMD1]

[ack]

 [DATA1]

[ack]

 ([CMD2]

[ack]

 [DATA2]

[ack]

… [CMDn]

[ack]

 

[DATAn]

[nak]

)