Intermec 073300-001 用户手册

ADDR DECODE,

RD/WR CTL

PCI

IRQ CTL

SD31..0

SA25..0

SCAN_IRQ

AD31..0

HCR_WR2*
HCR_WR5*

SDBUF_D7..0

SCAN_DREQ

Host CPU

I/F

Scanner

I/F

Mini-PCI Slot

o

GPIO

LogiCore

PCI Core

PAR

PERR#

SERR#

FRAME#

IRDY#

TRDY#

STOP#

DEVSEL#

RST#

PCI_CLK

REQ#, GNT#

C/BE#3..0

BUS

ARBITER

Initiator

Logic

RD FIFO

DQM3..0

nOE

nPWE

RDY

RD/WR

FPGA_CS

DBP_HSYNC

SOS_VSYNC

ILLUM_LASEN_RTS

SCAN_LED

SCAN_LED_LOW

TETH_DBP, SOS

TETH_PRESENT

WR FIFO

Target

Logic

RD FIFO

WR FIFO

SDRAM

Controller

USER_LED<2:1>

SCAN_TRIG*

Local

CPU

I/F

Logic

PCI

CTL

REGs

INTA#

INTB#

KEY_RET<7:0>

PCI_IRQ

BREQ, BGNT

PCI Bridge

Host I/F
Wrapper

nWE

SPEED_RANGE_GDRD

SCAN_FLASH_EN

DOCK_TRIG*

VOL<2:0>

ACT#, PME#

SDCS0

SDCAS

SDRAS

SDCLK

DLL

DLL

(/2)

FPGA_CLK

CLK_OUT

CLK

PCLK

IMAGER_PIXCLK

BATT_FAULT_IRQ

CLKRUN#

IDSEL

HCR/PCI_CS

IMAGE

CAPTURE

STATE

MACHINE

DMA

BUFFER

CTL

REGs

FIFO

DBP

COUNT

LOGIC

GPIO

IRQ
CTL

Kypd

Scanner I/F

IO MUX LOGIC

BLUR 

DETECT,

EXPOSURE

SENSE

Bus I/F

 

The bridge maps PCI bus memory, IO, and configuration space into 
PXA255 processor space in Memory Area 2. In this mode, the PXA255 
functions as the initiator, reading data from and writing data to the 
(target) PCI card as a memory-mapped device. The bridge also 
incorporates an SDRAM controller so that it can function as an alternate 
bus master. In this mode the PCI card is the initiator and the SDRAM in 
Partition 0 is the target.