Intel E7-8891 v2 CM8063601377422 用户手册

264

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

9:9

RW

0x0

override_socketid_in_cplid:

For TPH/DCA requests, the Completer ID can be returned with SocketID 

when this bit is set.

8:7

RV

-

Reserved.

6:6

RW

0x0

problematic_port_for_lock_flows:

This bit is set by BIOS when it knows that this port is connected to a device 

that creates Posted-Posted dependency on its In-Out queues. 
Briefly, this bit is set on a link if:
IIO lock flows depend on the setting of this bit to treat this port in a special 

way during the flows. Note that if BIOS is setting up the lock flow to be in 

the ’Intel

®

QPI compatible’ mode, then this bit must be set to 0.

Notes:
An inbound MSI request can block the posted channel until EOI’s are posted 

to all outbound queues enabled to receive EOI. Because of this, this bit 

cannot be set unless EOIFD is also set. 

5:5

RW

0x0

disable_mctp_broadcast_to_this_link:

When set, this bit will prevent a broadcast MCTP message (w/ Routing Type 

of ‘Broadcast from RC’) from being sent to this link.

4:4

RWS

0x0

formfactor:

Indicates what form-factor a particular root port controls
0 - CEM
1 - Express Module
This bit is used to interpret bit 6 in the VPP serial stream for the port as 

either MRL# (CEM) input or EMLSTS# (Express Module) input.

3:3

RW

0x0

override_system_error_on_pcie_fatal_error_enable:

When set, fatal errors on PCI Express (that have been successfully 

propagated to the primary interface of the port) are sent to the IIO core 

error logic (for further escalation) regardless of the setting of the equivalent 

bit in the ROOTCTRL register. When clear, the fatal errors are only 

propagated to the IIO core error logic if the equivalent bit in ROOTCTRL 

register is set.
For Dev#0 in DMI mode and Dev#3/Fn#0, unless this bit is set, DMI link 

related fatal errors will never be notified to system software. 

2:2

RW

0x0

override_system_error_on_pcie_non_fatal_error_enable:

When set, nonfatal errors on PCI Express (that have been successfully 

propagated to the primary interface of the port) are sent to the IIO core 

error logic (for further escalation) regardless of the setting of the equivalent 

bit in the ROOTCTRL register. When clear, the nonfatal errors are only 

propagated to the IIO core error logic if the equivalent bit in ROOTCTRL 

register is set.
For Dev#0 in DMI mode and Dev#3/Fn#0, unless this bit is set, DMI link 

related nonfatal errors will never be notified to system software.