Intel E7-8891 v2 CM8063601377422 用户手册

290

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

XP PM Response Control

The PMR register controls operation of its associated counter, and provides overflow or 
max compare status information. 

11:8

RW_V

0xf

high_nibble_pex_compare1_value:

High Nibble PEX Compare1 value  
High order bits [35:32] of the 36-bit PM Compare1 register. 

7:4

RV

-

Reserved.

3:0

RW_V

0xf

high_nibble_pex_compare0_value:

High Nibble PEX Compare0 value  
High order bits [35:32] of the 36-bit PM Compare0 register. 

31:31

RV

-

Reserved  

30:30

RW

0x0

not_greater_than_comparison:

Not greater than comparison  
0: PMC will compare a greater than function. When clear the perfmon status 

will assert when the PMD is greater than the PMC. 
1: PMC will compare with NOT (greater than) function. When set the perfmon 

status will assert when the PMD is less than or equal to the PMC. 

29:29

RW

0x0

force_pmd_counter_to_add_zero_to_input:

Force PMD counter to add zero to input  
This feature is used with the queue measurement bus. When this bit is set the 

value on the queue measurement bus is added to zero so the result in PMD will 

always reflect the value from the queue measurement bus.
0: Do not add zero. Normal PerfMon operation.
1: Add zero with input queue bus. 

28:28

RW

0x0

latched_count_enable_select:

Latched Count Enable Select  
0: Normal PM operation. Use CENS as count enable.
1: Use Latched count enable from queue empty events 

27:27

RW

0x0

reset_pulse_enable:

Reset Pulse Enable  
Setting this bit will select a pulsed version of the reset signal source in the 

reset block.
0: Normal reset signaling
1: Select a pulsed reset from the reset signal sources.