Intel SR1GZ CM8063601454907 用户手册
产品代码
CM8063601454907
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
435
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
14.8.26 VPPCTL
This register defines the control/command for PCA9555.
0:0
RW_LB
0x0
pin0:
This bit acts as the general purpose output for the Error[0] pin. Software
sets/clears this bit to assert/deassert Error[0] pin. This bit applies only when
ERRPINCTL[1:0] = 01; otherwise it is reserved.
0: Assert ERR#[0] pin (drive low)
1: Deassert ERR#[0] pin (float high)
1: Deassert ERR#[0] pin (float high)
Notes:
This pin is open drain and must be pulled high by external resistor when
This pin is open drain and must be pulled high by external resistor when
deasserted.
BIOS needs to write 1 to this bit for security reasons if this register is not
BIOS needs to write 1 to this bit for security reasons if this register is not
used.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xac
Bit
Attr
Default
Description
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5
Function:
2
Offset:
0xb0
Bit
Attr
Default
Description
63:60
RO
0x1
vpp_version:
Specified the version of this structure for BIOS use.
0: VPPCTL with 11 PCIe* ports.
1: VPPCTL with 11 PCIe* ports + VPPMEM with 4 memory ports.
0: VPPCTL with 11 PCIe* ports.
1: VPPCTL with 11 PCIe* ports + VPPMEM with 4 memory ports.
59:56
RV
-
Reserved
55:55
RWS
0x0
vpp_reset_mode:
0: Power good reset will reset the VPP state machines and hard reset will
cause the VPP state machine to terminate at the next ’logical’ VPP stream
boundary and then reset the VPP state machines
1: Both power good and hard reset will reset the VPP state machines
1: Both power good and hard reset will reset the VPP state machines
54:44
RWS
0x0
vpp_en:
When set, the VPP function for the corresponding root port is enabled.
Enable Root Port
[54] Port 3d
[53] Port 3c
[52] Port 3b
[51] Port 3a
[50] Port 2d
[49] Port 2c
[48] Port 2b
[47] Port 2a
[46] Unused
[45] Unused
[44] Port 0 (PCIe* mode only)
Enable Root Port
[54] Port 3d
[53] Port 3c
[52] Port 3b
[51] Port 3a
[50] Port 2d
[49] Port 2c
[48] Port 2b
[47] Port 2a
[46] Unused
[45] Unused
[44] Port 0 (PCIe* mode only)