Intel E7-4890 v2 CM8063601272412 用户手册
产品代码
CM8063601272412
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
291
Datasheet Volume Two: Functional Description, February 2014
Integrated I/O (IIO) Configuration Registers
26:22
RV
-
Reserved
21:21
RW
0x0
local_dft_event_select:
20:19
RW
0x0
event_group_selection:
Event Group Selection
Selects which event register to use for performance monitoring.00: Bus events
Selects which event register to use for performance monitoring.00: Bus events
(XPMEVL,H register) and also Resource Utilizations (XP_PMER Registers) when
all XP_PMEH and XP_PMEL Registers are set to ’0’. that is, When monitoring
PMER events, all PMEV events are to be deselected; when monitoring PMEV
events, all PMER events are to be deselected.
01: Reserved
10: Queue measurement (in the XPPMER register). Note: To enable FIFO
01: Reserved
10: Queue measurement (in the XPPMER register). Note: To enable FIFO
queue histogramming write bit field CNTMD =’11’ and select queues in the
XPPMER register.
11: Reserved
11: Reserved
18:17
RW
0x0
count_event_select:
Count Event Select
Selects the condition for incrementing the performance monitor counter.
00: Event source selected by PMEV{L,H}
01: Partner event status (max compare or overflow)
10: All clocks when enabled
11: Reserved
Selects the condition for incrementing the performance monitor counter.
00: Event source selected by PMEV{L,H}
01: Partner event status (max compare or overflow)
10: All clocks when enabled
11: Reserved
16:16
RW
0x0
event_polarity_invert:
Event Polarity Invert
This bit inverts the polarity of the conditioned event signal.
0: No inversion
1: Invert the polarity of the conditioned event signal
This bit inverts the polarity of the conditioned event signal.
0: No inversion
1: Invert the polarity of the conditioned event signal
15:14
RW
0x0
count_mode:
Count Mode
This field sets how the events will be counted.
00: Count clocks when event is logic high. Counting is level sensitive,
This field sets how the events will be counted.
00: Count clocks when event is logic high. Counting is level sensitive,
whenever the event is logic 1 the counter is enabled to count.
01: Count rising edge events. Active low signals should be inverted with
01: Count rising edge events. Active low signals should be inverted with
EVPOLINV for correct measurements.
10: Latch event and count clocks continuously. After the event is asserted,
10: Latch event and count clocks continuously. After the event is asserted,
latch this state and count clocks continuously. The latched state of this
condition is cleared by xxxPMRx.CNTRST bit, or PERFCON.GBRST, or GE[3:0].
11: Enable FIFO (push/pop) queue histogram measurement.
This mode will enable histogram measurements on PM0. This mode enable
11: Enable FIFO (push/pop) queue histogram measurement.
This mode will enable histogram measurements on PM0. This mode enable
logic to perform the function listed in the table below. The measurement cycle
will not begin until the Qempty signal is asserted. Refer to xref.
FIFO queue histogram table
FIFOn_Push.......FIFOn_POP............PMD Adder control
....0............................0........................Add zero
....1............................0........................Add queue bus value*
....0............................1........................Sub queue bus value*
....1............................1........................Add zero
The latched condition of the Qempty signal cannot be cleared by
FIFO queue histogram table
FIFOn_Push.......FIFOn_POP............PMD Adder control
....0............................0........................Add zero
....1............................0........................Add queue bus value*
....0............................1........................Sub queue bus value*
....1............................1........................Add zero
The latched condition of the Qempty signal cannot be cleared by
PMR.CLREVLAT. A new measurement cycle requires clearing all counters and
the latched value by asserting either PMRx.CNTRST or PERFCON.GBRST.
Type:
CFG
PortID:
N/A
Bus:
0
Device:
0Function:0
Bus:
0
Device:
2Function:0
Bus:
0
Device:
3Function:0
Offset:
0x494, 0x498
Bit
Attr
Default
Description