Transcend DDR3 4GB 1333 TS512MLK64V3NL 用户手册
产品代码
TS512MLK64V3NL
Features
•
RoHS compliant products.
•
JEDEC standard 1.5V ± 0.075V Power supply
•
VDDQ=1.5V ± 0.075V
•
Clock Freq: 667MHZ for 1333Mb/s/Pin.
•
Programmable CAS Latency: 6, 7, 8, 9
•
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
•
Programmable /CAS Write Latency (CWL)
=7 (DDR3-1333)
•
8 bit pre-fetch
•
Burst Length: 4, 8
•
Internal calibration through ZQ pin
•
On Die Termination with ODT pin
•
Serial presence detect with EEPROM
•
Asynchronous reset
Pin Identification
Symbol
Function
A0~A15, BA0~BA2
Address/Bank input
DQ0~DQ63
Bi-direction data bus.
DQS0~DQS7
Data strobes
/DQS0~/DQS7
Differential Data strobes
CK0, /CK0,CK1, /CK1
Clock Input. (Differential pair)
CKE0, CKE1
Clock Enable Input.
ODT0, ODT1
On-die termination control line
/S0, /S1
DIMM rank select lines.
/RAS
Row address strobe
/CAS
Column address strobe
/WE
Write Enable
DM0~DM7
Data masks/high data strobes
VDD
Core power supply
VDDQ
I/O driver power supply
V
REF
DQ
I/O reference supply
V
REF
CA
Command/address reference
supply
V
DD
SPD
SPD EEPROM power supply
SA0~SA2
Address select for EEPROM
SCL
Clock for EEPROM
SDA
Data for EEPROM
VSS
Ground
/RESET
Set DRAMs Known State
VTT
SDRAM I/O termination supply
NC
No Connection
DDR3 VLP Unbuffered DIMM is high-speed, low power memory module
that use DDR3 SDRAM in FBGA package and a 2048 bits serial
EEPROM on a 240-pin printed circuit board. DDR3 VLP Unbuffered
DIMM is a Dual In-Line Memory Module and is intended for mounting into
240-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system
clock. Data I/O transactions are possible on both edges of DQS. Range
of operation frequencies, programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance memory
system applications.
that use DDR3 SDRAM in FBGA package and a 2048 bits serial
EEPROM on a 240-pin printed circuit board. DDR3 VLP Unbuffered
DIMM is a Dual In-Line Memory Module and is intended for mounting into
240-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of system
clock. Data I/O transactions are possible on both edges of DQS. Range
of operation frequencies, programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance memory
system applications.
DDR3 VLP Unbuffered DIMM