Transcend 512MB DDR266 ECC Unbuffer Memory TS64MLD72V6J 用户手册
产品代码
TS64MLD72V6J
T
T
T
S
S
S
6
6
6
4
4
4
M
M
M
L
L
L
D
D
D
7
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7
2
2
2
V
V
V
6
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6
J
J
J
184PIN DDR266 Unbuffered DIMM
512MB With 64Mx8 CL2.5
Transcend Information Inc.
1
Description
The TS64MLD64V6J is a 64M x 72bits Double Data Rate
SDRAM high-density for DDR266.The TS64MLD64V6J
consists of 9pcs CMOS 64Mx8 bits Double Data Rate
SDRAMs in 66 pin TSOP-II 400mil packages and a 2048
bits serial EEPROM on a 184-pin printed circuit board.
The TS64MLD64V6J is a Dual In-Line Memory Module
and is intended for mounting into 184-pin edge connector
sockets.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges of DQS. Range of operation frequencies,
programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Features
• Power supply: VDD: 2.5V ± 0.1V, VDDQ: 2.5V ± 0.1V
• Max clock Freq: 133MHZ.
• Double-data-rate architecture; two data transfers per
• Max clock Freq: 133MHZ.
• Double-data-rate architecture; two data transfers per
clock cycle
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transition with CK transition
• Auto and Self Refresh 7.8us refresh interval.
• Data I/O transactions on both edge of data strobe.
• Edge aligned data output, center aligned data
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
• DLL aligns DQ and DQS transition with CK transition
• Auto and Self Refresh 7.8us refresh interval.
• Data I/O transactions on both edge of data strobe.
• Edge aligned data output, center aligned data
• Serial Presence Detect (SPD) with serial EEPROM
• SSTL-2 compatible inputs and outputs.
• MRS cycle with address key programs.
CAS Latency (Access from column address): 2.5
Burst Length (2,4,8)
Data Sequence (Sequential & Interleave)
Placement
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I
A
B
D
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G
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C
PCB: 09-1835