Intel Celeron M 420 1.60 GHz LF80538NE0251M 数据表
产品代码
LF80538NE0251M
Intel
®
Celeron
®
M Processor Datasheet
69
Debug Tools Specifications
6
Debug Tools Specifications
Please refer to the ITP700 Debug Port Design Guide and the platform design guides for
information regarding debug tools specifications.
6.1
Logic Analyzer Interface (LAI)
Intel is working with logic analyzer vendors to provide LAIs for use in debugging Intel
Celeron M
processor systems. The following information is general in nature. Specific information must be
obtained from the logic analyzer vendor.
Due to the complexity of Intel
Celeron M processor-based systems, the LAI is critical in providing
the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind
when designing a Intel
Celeron M processor-based system that can make use of an LAI:
mechanical and electrical.
6.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the Intel Celeron M processor. The LAI pins
plug into the socket, while the Intel Celeron M processor pins plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection between the
Intel Celeron M processor and a logic analyzer. The maximum volume occupied by the LAI,
known as the keepout volume, as well as the cable egress restrictions, should be obtained from the
logic analyzer vendor. System designers must make sure that the keepout volume remains
unobstructed inside the system.
6.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that their tool will work in the system. Contact the logic analyzer vendor for electrical
specifications and load models for the LAI solution they provide.