Intel Phi 7120A SC7120A 数据表
产品代码
SC7120A
Intel
®
Xeon Phi™ Coprocessor Datasheet
Document ID Number: 328209 003EN
12
sense monitoring for system fan and power control. This information is forwarded to
the coprocessor for power state control. The SMBus interface can be used by system
for chassis fan control with the passive heat sink card and for integration with the Node
Management controller in the platform. Communication with the system baseboard
management controller (BMC) or peripheral control hub (PCH) occurs over the SMBus
using the standard IPMB protocol. See chapter on manageability for more details.
the coprocessor for power state control. The SMBus interface can be used by system
for chassis fan control with the passive heat sink card and for integration with the Node
Management controller in the platform. Communication with the system baseboard
management controller (BMC) or peripheral control hub (PCH) occurs over the SMBus
using the standard IPMB protocol. See chapter on manageability for more details.
2.1.3
Intel
®
Xeon Phi™ Coprocessor Silicon
is a conceptual drawing of the general structure of the Intel
®
Xeon Phi™
coprocessor architecture, and does not imply actual distances, latencies, etc. The
cores, PCIe Interface logic, and GDDR5 memory controllers are connected via an
Interprocessor Network (IPN) ring, which can be thought of as independent
bidirectional ring.
cores, PCIe Interface logic, and GDDR5 memory controllers are connected via an
Interprocessor Network (IPN) ring, which can be thought of as independent
bidirectional ring.
The L2 caches are shown here as slices per core, but can also be thought of as a fully
coherent cache, with a total size equal to the sum of the slices. Information can be
copied to each core that uses it to provide the fastest possible local access, or a single
copy can be present for all cores to provide maximum cache capacity.
coherent cache, with a total size equal to the sum of the slices. Information can be
copied to each core that uses it to provide the fastest possible local access, or a single
copy can be present for all cores to provide maximum cache capacity.
The Intel® Xeon Phi™ coprocessor can support up to 61 cores (making a 30.5 MB L2)
cache) and 8 memory controllers with 2 GDDR5 channels each. The maximum number
of cores and total card memory varies with Intel® Xeon Phi™ coprocessor SKU; refer to
the Intel
cache) and 8 memory controllers with 2 GDDR5 channels each. The maximum number
of cores and total card memory varies with Intel® Xeon Phi™ coprocessor SKU; refer to
the Intel
®
Xeon Phi™ Coprocessor Specification Update for information.
Communication around the ring follows a Shortest Distance Algorithm (SDA). Co-
resident with each core structure is a portion of a distributed tag directory. These tags
are hashed to distribute workloads across the enabled cores. Physical addresses are
also hashed to distribute memory accesses across the memory controllers.
resident with each core structure is a portion of a distributed tag directory. These tags
are hashed to distribute workloads across the enabled cores. Physical addresses are
also hashed to distribute memory accesses across the memory controllers.
Figure 2-4.
Intel® Xeon Phi™ Coprocessor Silicon Layout
…
…
…
…
GDDR5
Memory
Controller
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
Coprocessor
Core
L2 Cache
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
GDDR5
Memory
Controller
IPN
PCIe
Interface
IPN