Acer E3-1220 v3 KC.12201.3E3 用户手册

This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The

128-bit BLT engine provides hardware acceleration of block transfers of pixel data for

many common Windows operations. The BLT engine can be used for the following:
•

Move rectangular blocks of data between memory locations

•

Data alignment

•

To perform logical operations (raster ops)

The rectangular block of data does not change, as it is transferred between memory

locations. The allowable memory transfers are between: cacheable system memory

and frame buffer memory, frame buffer memory and frame buffer memory, and within

system memory. Data to be transferred can consist of regions of memory, patterns, or

solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per

pixel.

The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits.

BLTs can be either opaque or transparent. Opaque transfers move the data specified

to the destination. Transparent transfers compare destination color to source color and

write according to the mode of transparency selected.

Data is horizontally and vertically aligned at the destination. If the destination for the

BLT overlaps with the source memory location, the BLT engine specifies which area in

memory to begin the BLT transfer. Hardware is included for all 256 raster operations

(source, pattern, and destination) defined by Microsoft*, including transparent BLT.

The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting

software to set up instruction buffers and use batch processing. The BLT engine can

perform hardware clipping during BLTs.

The processor supports simultaneous use of the Processor Graphics Controller (GT)

and a x16 PCI Express* Graphics (PEG) device. The processor supports a maximum of

2 displays connected to the PEG card in parallel with up to 2 displays connected to the

processor and PCH.

When supporting Multi Graphics Multi Monitors, "drag and drop" between monitors and

the 2x8PEG is not supported.

•

The processor supports:
— Three Digital Display (x4 DDI) interfaces that can be configured as

DisplayPort*, HDMI*, or DVI. DisplayPort* can be configured to use 1, 2, or 4

lanes depending on the bandwidth requirements and link data rate of RBR

(1.62 GT/s), HBR (2.7 GT/s) and HBR2 (5.4 GT/s). When configured as

HDMI*, DDIx4 port can support 2.97 GT/s. In addition, Digital Port D ( x4

DDI) interface can also be configured to carry embedded DisplayPort*

(eDPx4). Built-in displays are only supported on Digital Port D.

— One dedicated Intel FDI Port for legacy VGA support on the PCH.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

30

Order No.: 328907-001