Acer E3-1220 v3 KC.12201.3E3 用户手册

During S0 idle state, system memory may be conditionally placed into self-refresh

 for more details on conditional self-

refresh with Intel HD Graphics enabled.

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor core flushes pending cycles and then enters SDRAM ranks that are not

used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the

SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for package C3 or deeper power states as

long as there are no memory requests to service. The target usage is shown in the

following table.

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor core controller can be configured to put the devices in active power-

down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-

assertion with all pages closed). Pre-charge power-down provides greater power

savings but has a bigger performance impact, since all pages will first be closed before

putting the devices in power-down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered

down for unused ranks.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled, and any DLL circuitry

related ONLY to unused signals should be disabled. The input path must be gated to

prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

RAPL is a power and time constant pair. DRAM RAPL defines an average power

constraint for the DRAM domain. Constraint is controlled by the PCU. Platform entities

(PECI or in-band power driver) can specify a power limit for the DRAM domain. PCU

continuously monitors the extant of DRAM throttling due to the power limit and

rebudgets the limit between DIMMs.

Intel

®

 Xeon

®

 Processor E3-1200 v3 Product Family

Datasheet – Volume 1 of 2

June 2013

60

Order No.: 328907-001