Kingston Technology HyperX 2GB 800MHz DDR2 Non-ECC Ultra Low-Latency DIMM (Kit of 2) KHX6400D2ULK2/2G 产品宣传页
产品代码
KHX6400D2ULK2/2G
Memory Module Specification
Document No. 4804756-001.A00
06/12/07
KHX6400D2ULK2/2G
2GB (1GB 128M x 64-Bit x 2 pcs.)
PC2-6400 CL3 240-Pin DIMM Kit
KEYED
Page 1
DESCRIPTION:
Kingston's KHX6400D2ULK2/2G is a kit of two ultra low-latency 128M x 64-bit 1GB (1024MB)
DDR2-800 CL3 SDRAM (Synchronous DRAM) memory modules, based on sixteen 64M x 8-bit
DDR2 FBGA components per module. Total kit capacity is 2GB (2048MB). Each module pair has
been tested to run at DDR2 800MHz at low latency timing of 3-3-3-10 at 2.3-2.35V. The SPD is
programmed to JEDEC standard latency 800Mhz timing of 5-5-5-15 at 1.8V. Each 240-pin DIMM
uses gold contact fingers and requires +1.8V. The electrical and mechanical specifications are as
follows:
DDR2-800 CL3 SDRAM (Synchronous DRAM) memory modules, based on sixteen 64M x 8-bit
DDR2 FBGA components per module. Total kit capacity is 2GB (2048MB). Each module pair has
been tested to run at DDR2 800MHz at low latency timing of 3-3-3-10 at 2.3-2.35V. The SPD is
programmed to JEDEC standard latency 800Mhz timing of 5-5-5-15 at 1.8V. Each 240-pin DIMM
uses gold contact fingers and requires +1.8V. The electrical and mechanical specifications are as
follows:
FEATURES:
Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 3, 4, 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 800MHz 5-5-5-15 at +1.8V / 800MHz 3-3-3-10 at +2.3-2.35V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Differential clock inputs (CK and CK)
DLL aligns DQ and DQS transition with CK transition
Programmable Read latency 3, 4, 5 (clock)
Burst Length: 4, 8 (Interleave/nibble sequential)
Programmable Burst type (sequential & interleave)
Timing Reference: 800MHz 5-5-5-15 at +1.8V / 800MHz 3-3-3-10 at +2.3-2.35V
Edge aligned data output, center aligned data input
Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh)
Serial presence detect with EEPROM
High Performance Heat Spreader
PCB : Height 1.180” (30.00mm), double sided component
PERFORMANCE:
Clock Cycle Time (tCK) CL=5
2.5ns (min.) / 8ns (max.)
Row Cycle Time (tRC)
57.5ns (min.)
Refresh to Active/Refresh Command Time (tRFC)
105ns
Row Active Time (tRAS)
45ns (min.) / 70,000ns (max.)
Single Power Supply of
+1.8V (+/- .1V)
Power
1.922 W (operating per module)
UL Rating
94 V - 0
Operating Temperature
0
o
C to 55
o
C
Storage Temperature
-55
o
C to +125
o
C
T E C H N O L O G Y