Intel E7-4870 v2 CM8063601272606 用户手册
产品代码
CM8063601272606
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
111
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
13.2.2.2
SPAREADDRESSLO
Spare Address Low
Always points to the lower address for the next sparing operation. This register will not
be affected by the HA access to the spare source rank during the HA window.
be affected by the HA access to the spare source rank during the HA window.
29:25
RO
0x0
Interrupt Message Number (interrupt_message_number):
N/A for this device
24:24
RO
0x0
Slot Implemented (slot_implemented):
N/A for integrated endpoints
23:20
RO
0x9
Device/Port Type (device_port_type):
Device type is Root Complex Integrated Endpoint
19:16
RO
0x1
Capability Version (capability_version):
PCI Express Capability is Compliant with Version 1.0 of the PCI Express
Spec.
Note:
This capability structure is not compliant with Versions beyond 1.0, since
This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only purpose
for this capability structure is to make enhanced configuration space
available. Minimizing the size of this structure is accomplished by reporting
version 1.0 compliancy and reporting that this is an integrated root port
device. As such, only three Dwords of configuration space are required for
this structure.
15:8
RO
0x0
Next Capability Pointer (next_ptr):
Pointer to the next capability. Set to 0 to indicate there are no more
capability structures.
7:0
RO
0x10
Capability ID (capability_id):
Provides the PCI Express capability ID assigned by PCI-SIG.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0x40
Bit
Attr
Default
Description
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0x80
Bit
Attr
Default
Description
31:31 RV
-
Reserved.
30:0
RW_LV
0x0
RANKADD (rankadd):
Always points to the lower address for the next sparing operation. This register
will not be affected by the HA access to the spare source rank during the HA
window.