Texas Instruments LM3549 Evaluation Board LM3549SQEV/NOPB LM3549SQEV/NOPB 数据表
产品代码
LM3549SQEV/NOPB
S
W
Slave Address
(7 bits)
Control Register Add.
(8 bits)
A
A
A
Register Data
(8 bits)
P
From Master to Slave
From Slave to Master
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
P - STOP CONDITION
W - WRITE
W - WRITE
SDA
SCL
S
P
S
TART condition
STO
P
condition
SCL
SDA
data
change
allowed
data valid
data
change
allowed
data valid
data
change
allowed
SNVS640A – AUGUST 2010 – REVISED MAY 2013
I
2
C VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of
the data line can only be changed when CLK is LOW.
the data line can only be changed when CLK is LOW.
Figure 21. I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I
2
C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA
transitioning from LOW to HIGH while SCL is HIGH. The I
transitioning from LOW to HIGH while SCL is HIGH. The I
2
C master always generates START and STOP bits.
The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I
transmission, I
2
C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
Figure 22. Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the ninth clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the ninth clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LM3549 address is 36 hex. For the eighth bit, a “0” indicates a
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
Figure 23. I
2
C Write Cycle
14
Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links: