Texas Instruments Evaluation Module for 1A Positive Fixed Voltage Linear Regulator TLV1117LV33EVM-714 TLV1117LV33EVM-714 数据表

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–

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This User

’

s Guide describes operational use of the TLV1117LVxxEVM-714 Evaluation Module (EVM) as a

reference design for engineering demonstration and evaluation of the TLV1117LVxx, low dropout linear
regulator (LDO). Included in this user

’

s guide are setup instructions, a schematic diagram, layout and

thermal guidelines, a bill of materials, and test results.

1

Introduction

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2

Setup

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2.1

Input/Output Connectors and Jumper Descriptions

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2.2

Soldering Guidelines

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2.3

Equipment Setup

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3

Operation

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4

Test Results

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4.1

Turn-on Sequence

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4.2

Output Load Transient

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5

Thermal Guidelines and Layout Recommendations

...................................................................

6

Board Layout

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7

Bill of Material

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1

Turn-on Sequence: Green

–

V

IN

(3.3 V), Blue

–

I

O

Ramp, Yellow

–

V

O

Ramp

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2

Load step and Transient Response: Yellow

–

V

OUT

, Green

–

V

IN

, Blue

–

Output Current, I

O

......................

3

Assembly Layer

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4

Top Layer Routing

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5

Bottom Layer Routing

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6

TLV1117LVxxEVM-714 Schematic

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1

Thermal Resistance,

θ

JA

, and Maximum Power Dissipation

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2

TLV1117LVxxEVM-714 Bill of Materials

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The Texas Instruments TLV1117LVxxEVM-714 EVM helps design engineers to evaluate the operation
and performance of the TLV1117LVxx family of linear regulators for possible use in their own circuit
application. This particular EVM configuration contains a single linear regulator with internal thermal and
current limit shutdowns circuitry in a small SOT-223 package. The regulator is capable of delivering up to
1A to the load depending on the input-output power dissipation across the part which can be minimized
because of the very low dropout voltage. The input and output capacitors for the TLV1117LVxx need be
0.4

µ

F (effective minimum) for stability; however, for conservative design practice accounting for widely

varying noise environments, and dynamic line/load conditions, a 10-

µ

F capacitor has been employed at

the input and output ports.

1

SLVU449B

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March 2011

–

Revised May 2011

Copyright

©

2011, Texas Instruments Incorporated