Texas Instruments Evaluation Board for the LP38512 LP38512TJ-ADJEV LP38512TJ-ADJEV 数据表
产品代码
LP38512TJ-ADJEV
User's Guide
SNVA331B – January 2009 – Revised April 2013
AN-1802 LP38512TJ-ADJ Evaluation Board
1
Introduction
This board is designed to allow the evaluation of the LP38512TJ-ADJ voltage regulator. Each board is
assembled and tested in the factory. This evaluation board has the TO-263 THIN 5-lead package
mounted, and the output voltage is set to 1.20 V.
assembled and tested in the factory. This evaluation board has the TO-263 THIN 5-lead package
mounted, and the output voltage is set to 1.20 V.
2
General Description
The LP38512TJ-ADJ is an adjustable LDO linear regulator capable of suppling up to 1.5A of output
current, and incorporates an Enable.
current, and incorporates an Enable.
The device has been designed to work with 10 µF input and output ceramic capacitors. Footprints areas
for C
for C
IN
and C
OUT
will allow for a variety of sizes.
3
Operation
The input voltage, applied between V
IN
and GND, must be no less than 2.25 V, which is the low end of the
operating range voltage, no greater than 5.5 V, which is the high end of the operating range voltage.
The input voltage should also be at least 500 mV greater than the set V
OUT
.
Loads can be connected to V
OUT
with reference to GND.
V
OUT
and V
IN
test points are provided on the board to allow accurate measurements directly onto the input
and output pins of the device, eliminating any voltage drop on the PCB traces or connecting wires to the
load.
load.
4
Setting V
OUT
The output voltage is set using the external resistive divider R1 and R2. The output voltage is given by the
formula:
formula:
V
OUT
= V
ADJ
x (1 + (R1 / R2) )
(1)
It is recommended that the values selected for R1 and R2 are such that the parallel value is less than 1.00
k
k
Ω
. This is to prevent internal parasitic capacitances on the ADJ pin from interfering with the F
Z
pole set
by R1 and C
FF
.
( (R1 x R2) / (R1 + R2) )
≤
1.00 k
Ω
(2)
lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%
capacitor values for C
FF
, for a range of V
OUT
values. Other values of R1, R2, and C
FF
are available that will
give similar results.
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1
SNVA331B – January 2009 – Revised April 2013
AN-1802 LP38512TJ-ADJ Evaluation Board
Copyright © 2009–2013, Texas Instruments Incorporated