Texas Instruments DAC8568EVM - DAC8568 Evaluation Module DAC8568EVM DAC8568EVM 数据表
产品代码
DAC8568EVM
EVM Operation
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5.2
Reference In/Out
The DAC8568, DAC8168, and DAC7568 provide the ability to use an internal reference or an external
reference in the range of 0 V to 2.5 V. The DACxx58 internal reference is powered OFF by default. The
following sections describe how to apply an external reference or use the internal reference.
reference in the range of 0 V to 2.5 V. The DACxx58 internal reference is powered OFF by default. The
following sections describe how to apply an external reference or use the internal reference.
5.2.1
External Reference
provides an external reference via JP3 (shorted pins 1-2 by default) from U2, a precision REF5025 source
of 2.5 VDC. When JP3 is shorted on pins 2-3, an external reference may be applied to J2 pin 20 or TP3
reference to TP2.
of 2.5 VDC. When JP3 is shorted on pins 2-3, an external reference may be applied to J2 pin 20 or TP3
reference to TP2.
These external reference sources are applied to pin 8 of the DAC installed on the EVM and are also fed to
U3, a unity gain buffer configured OPA379. The output of U3 may be used to provide a 2.5-V,
common-mode input to external signal-conditioning circuits via J2 pin 15.
U3, a unity gain buffer configured OPA379. The output of U3 may be used to provide a 2.5-V,
common-mode input to external signal-conditioning circuits via J2 pin 15.
5.2.2
Internal Reference
The internal reference can be powered up and powered down by using a serial command that requires a
32-bit write sequence as defined in the device data sheet (see the Serial Interface section and Table 1 of
document
32-bit write sequence as defined in the device data sheet (see the Serial Interface section and Table 1 of
document
).
CAUTION
Before enabling the internal reference of the DAC installed on the evaluation
board, ensure that any shunt jumper applied to JP3 is completely removed.
board, ensure that any shunt jumper applied to JP3 is completely removed.
The internal reference is enabled by setting the feature bits of the DAC control register. The
DAC7568/8168/8568 data sheet provides specific details on both the static and flexible operating modes
of the internal reference. For more information on using the internal reference source, review the Internal
Reference section of document
DAC7568/8168/8568 data sheet provides specific details on both the static and flexible operating modes
of the internal reference. For more information on using the internal reference source, review the Internal
Reference section of document
The internal reference source is applied to U3, a unity gain buffer configured OPA379. The output of U3
may be used to provide a 2.5-V, common-mode input to external signal conditioning circuits via J2 pin 15.
may be used to provide a 2.5-V, common-mode input to external signal conditioning circuits via J2 pin 15.
5.3
Digital Control
The digital control signals can be applied directly to J1 (top or bottom side). The DACxx68EVM also can
be connected directly to a DSP or microcontroller capable of supplying the necessary serial control inputs.
Visit the product folder for the EVM or the installed device for a current list of compatible interface and/or
accessory boards.
be connected directly to a DSP or microcontroller capable of supplying the necessary serial control inputs.
Visit the product folder for the EVM or the installed device for a current list of compatible interface and/or
accessory boards.
5.4
SYNC
For synchronous DAC update operations, jumper JP5 is provided to allow the source selection of the
signal applied to the SYNC input of the DAC installed on the EVM. The factory default condition for the
EVM is to place a shunt jumper between pins 1-2 of JP5. This allows the Frame Sync (FS) signal from
DSP host systems to be used as the SYNC input to the DAC. This signal originates from J1.7. When the
shunt on JP5 is moved to pins 2-3, a GPIO input applied via J1.1 can be used to control the SYNC input
to the DAC. JP2 may also be used to hold the LDAC input to the DAC low, allowing synchronous DAC
output updates.
signal applied to the SYNC input of the DAC installed on the EVM. The factory default condition for the
EVM is to place a shunt jumper between pins 1-2 of JP5. This allows the Frame Sync (FS) signal from
DSP host systems to be used as the SYNC input to the DAC. This signal originates from J1.7. When the
shunt on JP5 is moved to pins 2-3, a GPIO input applied via J1.1 can be used to control the SYNC input
to the DAC. JP2 may also be used to hold the LDAC input to the DAC low, allowing synchronous DAC
output updates.
5.5
LOAD DAC (LDAC)
For asynchronous updates to the DAC outputs, jumper JP6 is provided to allow the source selection of the
signal applied to the LDAC input of the DAC installed on the EVM. The factory default condition for the
EVM is to place a shunt jumper between pins 1-2 of JP6. This allows the Timer Output (TOUT) signal from
DSP host systems to be used as the LDAC input to the DAC. This signal originates from J1.17.
signal applied to the LDAC input of the DAC installed on the EVM. The factory default condition for the
EVM is to place a shunt jumper between pins 1-2 of JP6. This allows the Timer Output (TOUT) signal from
DSP host systems to be used as the LDAC input to the DAC. This signal originates from J1.17.
4
DACxx68EVM
SLAU301 – November 2009
Copyright © 2009, Texas Instruments Incorporated