Texas Instruments TPS658643EVM-752 Evaluation Module TPS658643EVM-752 TPS658643EVM-752 数据表
产品代码
TPS658643EVM-752
User's Guide
SLVU582A – December 2011 – Revised May 2012
TPS658643 System Evaluation Board
This user’s guide describes the characteristics, operation, and use of the TPS658643EVM-752 evaluation
module (EVM). The TPS658643EVM-752 is a fully assembled and tested platform for evaluating the
performance of the TPS658643 single-chip, power management device. This document includes
schematic diagrams, a printed-circuit board layout, bill of materials, and test data.
module (EVM). The TPS658643EVM-752 is a fully assembled and tested platform for evaluating the
performance of the TPS658643 single-chip, power management device. This document includes
schematic diagrams, a printed-circuit board layout, bill of materials, and test data.
Contents
1
Introduction
..................................................................................................................
1.1
Features
.............................................................................................................
1.2
Applications
.........................................................................................................
1.3
Requirements
.......................................................................................................
2
Electrical Performance Specifications
....................................................................................
3
Schematic
....................................................................................................................
4
Connector and Test Point Descriptions
..................................................................................
4.1
Headers and Switches
............................................................................................
4.2
Jumpers
.............................................................................................................
5
Setup
........................................................................................................................
6
TPS658643EVM Test Data
..............................................................................................
6.1
Operation Waveforms
............................................................................................
7
EVM Assembly Drawings and Layout
..................................................................................
8
Bill of Materials
.............................................................................................................
List of Figures
1
HPA752A Schematic, Sheet 1
............................................................................................
2
HPA752A Schematic, Sheet 2
............................................................................................
3
HPA752A Schematic, Sheet 3
............................................................................................
4
HPA752A Schematic, Sheet 4
............................................................................................
5
SM0, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div
............................................
6
SM1, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div
............................................
7
SM2, Ch. 1 - VIN 1 V/div; Ch. 2 - SW 1 V/div; Ch. 3 - Vout 10 mV/div
............................................
8
SM0, SM1, SM2, and LDO1 Start-Up
..................................................................................
9
LDO1, LDO2, LDO3, and LDO4 Start-Up
..............................................................................
10
LDO4, LDO5, and LDO9 Start-Up
.......................................................................................
11
32-kHz Clock
...............................................................................................................
12
Top Assembly – Silkscreen
..............................................................................................
13
Top Layer
...................................................................................................................
14
Layer 2
......................................................................................................................
15
Layer 3
......................................................................................................................
16
Layer 4
......................................................................................................................
17
Layer 5
......................................................................................................................
18
Layer 6
......................................................................................................................
19
Bottom Layer
...............................................................................................................
List of Tables
1
SLVU582A – December 2011 – Revised May 2012
TPS658643 System Evaluation Board
Copyright © 2011–2012, Texas Instruments Incorporated