Texas Instruments LMK01000 Evaluation Board LMK01000EVAL/NOPB LMK01000EVAL/NOPB 数据表
产品代码
LMK01000EVAL/NOPB
SNAS437G – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2. Default Register Settings after Power-on-Reset (continued)
Default
Bit
Bit Name
Bit State
Bit Description
Register
Bit Value
Location
CLKoutX_MUX
0
Bypassed
CLKoutX mux mode
18:17
CLKoutX_EN
0
Disabled
CLKoutX enable
16
R0 to R7
CLKoutX_DIV
1
Divide by 2
CLKoutX clock divide
15:8
CLKoutX_DLY
0
0 ps
CLKoutX clock delay
7:4
CLKin_SELECT
0
CLKin1
Select CLKin0 or CLKin1
29
EN_CLKout_Global
1
Normal - CLKouts normal
Global clock output enable
R14
27
POWERDOWN
0
Normal - Device active
Device power down
26
Reset Bit -- R0 only
This bit is only in register R0. The use of this bit is optional and it should be set to '0' if not used. Setting this bit
to a '1' forces all registers to their power-on-reset condition and therefore automatically clears this bit. If this bit is
set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and
RESET = 0.
to a '1' forces all registers to their power-on-reset condition and therefore automatically clears this bit. If this bit is
set, all other R0 bits are ignored and R0 needs to be programmed again if used with its proper values and
RESET = 0.
CLKoutX_MUX[1:0] -- Clock Output Multiplexers
These bits control the Clock Output Multiplexer for each clock output. Changing between the different modes
changes the blocks in the signal path and therefore incurs a delay relative to the Bypassed mode. The different
MUX modes and associated delays are listed below.
changes the blocks in the signal path and therefore incurs a delay relative to the Bypassed mode. The different
MUX modes and associated delays are listed below.
CLKoutX_MUX[1:0]
Mode
Added Delay Relative to Bypassed Mode
0
Bypassed (default)
0 ps
1
Divided
100 ps
400 ps
2
Delayed
(In addition to the programmed delay)
500 ps
3
Divided and Delayed
(In addition to the programmed delay)
CLKoutX_DIV[7:0] -- Clock Output Dividers
These bits control the clock output divider value. In order for these dividers to be active, the respective
CLKoutX_MUX (See Section 2.3.2) bit must be set to either "Divided" or "Divided and Delayed" mode. After all
the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are
aligned (See Section 1.5). By adding the divider block to the output path a fixed delay of approximately 100 ps is
incurred.
CLKoutX_MUX (See Section 2.3.2) bit must be set to either "Divided" or "Divided and Delayed" mode. After all
the dividers are programed, the SYNC* pin must be used to ensure that all edges of the clock outputs are
aligned (See Section 1.5). By adding the divider block to the output path a fixed delay of approximately 100 ps is
incurred.
The actual Clock Output Divide value is twice the binary value programmed as listed in the table below.
CLKoutX_DIV[7:0]
Clock Output Divider value
0
0
0
0
0
0
0
0
Invalid
0
0
0
0
0
0
0
1
2 (default)
0
0
0
0
0
0
1
0
4
0
0
0
0
0
0
1
1
6
0
0
0
0
0
1
0
0
8
0
0
0
0
0
1
0
1
10
.
.
.
.
.
.
.
.
...
1
1
1
1
1
1
1
1
510
12
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