Texas Instruments LMK00308 Evaluation Board LMK00308EVM/NOPB LMK00308EVM/NOPB 数据表
产品代码
LMK00308EVM/NOPB
March 2012
LMK00308EVM User’s Guide
5
Table 2: Input Selection
Selected Input
Default Input Mode
S1[6] CLKin_Sel1 State
S1[7] CLKin_Sel0 State
CLKin0/0*
Differential clock
OFF
OFF
CLKin1/1*
Differential clock
OFF
ON
OSCin
25 MHz XTAL onboard
ON
Don’t care
4. Connect and measure any clock output SMA labeled CLKoutA#/A#*, CLKoutB#/B#*, or REFout to an
oscilloscope or other test instrument using SMA cable(s). The output clock will be a level-translated/buffered
copy of the selected clock input or crystal oscillator. Note: All output clocks are AC-coupled to the SMA
connectors to ensure safe use with RF instruments.
Note: Any active output trace(s) without proper load termination can cause signal reflections on the board,
which can couple onto nearby outputs and degrade signal quality and measurement accuracy. To minimize
these effects, be sure to properly terminate any unused output trace with a 50-ohm SMA load, or else
disconnect any unused output trace from the device output pin by removing the series 0-ohm resistor. An
unused output or output bank may also be disabled using the output mode control switch.
copy of the selected clock input or crystal oscillator. Note: All output clocks are AC-coupled to the SMA
connectors to ensure safe use with RF instruments.
Note: Any active output trace(s) without proper load termination can cause signal reflections on the board,
which can couple onto nearby outputs and degrade signal quality and measurement accuracy. To minimize
these effects, be sure to properly terminate any unused output trace with a 50-ohm SMA load, or else
disconnect any unused output trace from the device output pin by removing the series 0-ohm resistor. An
unused output or output bank may also be disabled using the output mode control switch.
4. Signal Path and Control Switches
The LMK00308 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin, has
an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external
single-ended clock. To achieve the maximum operating frequency and lowest additive jitter, it is
recommended to use a differential input clock with high slew rate (>3 V/ns) on either CLKin0 or CLKin1 port.
The device provides up to 8 differential outputs with pin-selectable output mode (LVPECL, LVDS, HCSL, or
Hi-Z). An additional output, REFout, has a fixed LVCMOS buffer with output enable input.
All control pins are configured with the control DIP switch, S1. The input selection logic is shown in
an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an external
single-ended clock. To achieve the maximum operating frequency and lowest additive jitter, it is
recommended to use a differential input clock with high slew rate (>3 V/ns) on either CLKin0 or CLKin1 port.
The device provides up to 8 differential outputs with pin-selectable output mode (LVPECL, LVDS, HCSL, or
Hi-Z). An additional output, REFout, has a fixed LVCMOS buffer with output enable input.
All control pins are configured with the control DIP switch, S1. The input selection logic is shown in
The output mode selection logic for Bank A and Bank B are shown in
and
. The REFout
Table 3: Bank A Output Mode Selection
Bank A Output Mode
S1[3] CLKoutA_Type1 State
S1[4] CLKoutA_Type0 State
LVPECL
OFF
OFF
LVDS
OFF
ON
HCSL
ON
OFF
Disabled/Hi-Z
ON
ON
Table 4: Bank B Output Mode Selection
Bank B Output Mode
S1[1] CLKoutB_Type1 State
S1[2] CLKoutB_Type0 State
LVPECL
OFF
OFF
LVDS
OFF
ON
HCSL
ON
OFF
Disabled/Hi-Z
ON
ON
Table 5: REFout Enable Selection
REFout Enable Mode
S1[5] REFout_EN State
Disabled/Hi-Z
OFF
Enabled
ON