Texas Instruments LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input LMK00105BEVAL/NOP LMK00105BEVAL/NOPB 数据表
产品代码
LMK00105BEVAL/NOPB
SEL
OE
5 LVCMOS
Outputs
Outputs
Crystal
Universal Input
(Differential/
Single Ended)
Bank A
Bank B
CLKout0
CLKout1
CLKout2
CLKout3
CLKout4
SYNC
SNAS579F – MARCH 2012 – REVISED MAY 2013
LMK00105 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input
Check for Samples:
1
FEATURES
TARGET APPLICATIONS
2
•
5 LVCMOS Outputs, DC to 200 MHz
•
LO Reference Distribution for RRU
Applications
Applications
•
Universal Input
•
SONET, Ethernet, Fibre Channel Line Cards
–
LVPECL
•
Optical Transport Networks
–
LVDS
•
GPON OLT/ONU
–
HCSL
•
Server and Storage Area Networking
–
SSTL
•
Medical Imaging
–
LVCMOS / LVTTL
•
Portable Test and Measurement
•
Crystal Oscillator Interface
•
High-end A/V
–
Crystal Input Frequency: 10 to 40 MHz
•
Output Skew: 6 ps
DESCRIPTION
•
Additive Phase Jitter
The LMK00105 is a high performance, low noise
–
30 fs at 156.25 MHz (12 kHz to 20 MHz)
LVCMOS fanout buffer which can distribute 5 ultra-
low jitter clocks from a differential, single ended, or
low jitter clocks from a differential, single ended, or
•
Low Propagation Delay
crystal input. The LMK00105 supports synchronous
•
Operates with 3.3 or 2.5 V Core Supply Voltage
output enable for glitch free operation. The ultra low-
•
Adjustable Output Power Supply
skew, low-jitter, and high PSRR make this buffer
–
1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank
ideally suited for various networking, telecom, server
and storage area networking, RRU LO reference
and storage area networking, RRU LO reference
•
24 pin WQFN package (4.0 x 4.0 x 0.8 mm)
distribution, medical and test equipment applications.
The core voltage can be set to 2.5 or 3.3 V, while the
output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V.
The LMK00105 can be easily configured through pin
programming.
output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V.
The LMK00105 can be easily configured through pin
programming.
FUNCTIONAL BLOCK DIAGRAM
1
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
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PRODUCTION DATA information is current as of publication date.
Copyright © 2012–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.