Texas Instruments RM46 Hercules Safety MCU controlCARD TMDXRM46CNCD TMDXRM46CNCD 数据表
产品代码
TMDXRM46CNCD
SPNS184A – SEPTEMBER 2012 – REVISED SEPTEMBER 2013
RM46Lx50 16- and 32-Bit RISC Flash Microcontroller
Check for Samples:
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RM46Lx50 16- and 32-Bit RISC Flash Microcontroller
1.1
Features
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• High-Performance Microcontroller for Safety-
• Enhanced Timing Peripherals for Motor Control
Critical Applications
– 7 Enhanced Pulse Width Modulator (ePWM)
– Dual CPUs Running in Lockstep
Modules
– ECC on Flash and RAM Interfaces
– 6 Enhanced Capture (eCAP) Modules
– Built-In Self-Test for CPU and On-chip RAMs
– 2 Enhanced Quadrature Encoder Pulse
(eQEP) Modules
– Error Signaling Module with Error Pin
• Two High-End Timer (N2HETs) Modules
– Voltage and Clock Monitoring
– N2HET1: 32 Programmable Channels
• ARM® Cortex™ – R4F 32-Bit RISC CPU
– N2HET2: 18 Programmable Channels
– 1.66 DMIPS/MHz with 8-Stage Pipeline
– 160-Word Instruction RAM with Parity
– FPU with Single- and Double-Precision
Protection Each
– 12-Region Memory Protection Unit
– Each N2HET Includes Hardware Angle
– Open Architecture with Third-Party Support
Generator
• Operating Conditions
– Dedicated Transfer Units (HTU) on N2HETs
– 200-MHz System Clock
• Two 10- and 12-Bit Multibuffered Analog-to-
– Core Supply Voltage (VCC): 1.14 to 1.32 V
Digital Converter (MibADC) Modules
– I/O Supply Voltage (VCCIO): 3.0 to 3.6 V
– ADC1: 24 Channels
• Integrated Memory
– ADC2: 16 Channels Shared with ADC1
– Up to 1.25MB of Program Flash with ECC
– 64 Result Buffers with Parity Protection Each
– Up to 192KB of RAM with ECC
• Multiple Communication Interfaces
– 64KB of Flash for Emulated EEPROM with
– 10/100 Mbps Ethernet MAC (EMAC)
ECC
•
IEEE 802.3 Compliant (3.3-V I/O Only)
• 16-Bit External Memory Interface (EMIF)
•
Supports MII, RMII and MDIO
• Common Platform Architecture
– USB
– Consistent Memory Map Across Family
•
2-Port USB Host Controller
– Real-Time Interrupt (RTI) Timer (OS Timer)
•
One Full-Speed USB Device Port
– 128-Channel Vectored Interrupt Module (VIM)
– Three CAN Controllers (DCANs)
– 2-Channel Cyclic Redundancy Checker
•
64 Mailboxes with Parity Protection Each
(CRC)
•
Compliant to CAN Protocol Version 2.0A
• Direct Memory Access (DMA) Controller
and 2.0B
– 16 Channels and 32 Control Packets
– Inter-Integrated Circuit (I
2
C)
– Parity Protection for Control Packet RAM
– Three Multibuffered Serial Peripheral
– DMA Accesses Protected by Dedicated MPU
Interface (MibSPI) Modules
• Frequency-Modulated Phase-Locked Loop
•
128 Words with Parity Protection Each
(FMPLL) with Built-In Slip Detector
•
8 Transfer Groups
• Separate Nonmodulating PLL
– Up to Two Standard Serial Peripheral
• IEEE 1149.1 JTAG, Boundary Scan and ARM
Interface (SPI) Modules
CoreSight™ Components
– Two UART (SCI) Interfaces, One with Local
• Advanced JTAG Security Module (AJSM)
Interconnect Network (LIN 2.1) Interface
• Trace and Calibration Capabilities
Support
– Parameter Overlay Module (POM)
• Packages
• Sixteen General-Purpose Input/Output (GPIO)
– 144-Pin Quad Flatpack (PGE) [Green]
Pins Capable of Generating Interrupts
– 337-Ball Grid Array (ZWT) [Green]
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Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2012–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
processing does not necessarily include testing of all parameters.