Texas Instruments Evaluation Module for TPS7A7200 Low-Dropout Linear Regulator TPS7A7200EVM-718 TPS7A7200EVM-718 数据表
产品代码
TPS7A7200EVM-718
Thermal Guidelines and Layout Recommendations
5
Thermal Guidelines and Layout Recommendations
Thermal management is a key consideration in the design of any dc-dc converter but is especially
important for an LDO regulator when the power dissipation is high. Use
important for an LDO regulator when the power dissipation is high. Use
to approximate the
worst-case junction temperature for the application:
T
J
= T
A
+ P
d
x
θ
JA
(1)
where T
J
is the junction temperature (°C), TA is the ambient temperature (°C), P
d
is the power dissipation
in the device (W), and
θ
JA
is the thermal resistance from junction to ambient (°C/W). The maximum silicon
junction temperature must not be allowed to exceed 125°C for reliable operation. The layout design must
use copper trace and plane areas smartly, as thermal sinks, so as to not allow T
use copper trace and plane areas smartly, as thermal sinks, so as to not allow T
J
to exceed the absolute
maximum rating under all load, voltage, and temperature conditions for a given application.
The designer must carefully consider the thermal design of the printed-circuit board (PCB) for optimal
performance over temperature. For this EVM,
performance over temperature. For this EVM,
shows that the RGW package footprint employs a
square thermal pad, centered under the device, for conducting heat to the copper-spreading layers of the
PCB. The thermal pad is soldered directly to a pad on the PCB containing a 5x5 pattern of 10-mil vias for
conducting heat to the bottom-side ground plane copper. Approximately 4 in
PCB. The thermal pad is soldered directly to a pad on the PCB containing a 5x5 pattern of 10-mil vias for
conducting heat to the bottom-side ground plane copper. Approximately 4 in
2
of 2-oz copper is used on
the bottom side of the EVM for dissipating heat generated by the LDO regulator.
is based on thermal resistance information from the Thermal Information Table of the TPS7A7x00
data sheet for comparison with the approximate thermal resistance,
θ
JA
, calculated for this EVM layout to
show the variation in junction-ambient thermal resistances for varying copper areas. The High-K thermal
resistance,
resistance,
θ
JA
, is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x
3-inch with two 1-oz internal power and ground planes and one 2-oz copper bottom plane for
spreading/sinking heat from the IC component.
spreading/sinking heat from the IC component.
Table 1. Thermal Resistance,
θ
JA
, and Maximum Power Dissipation
Max Dissipation
Maximum Dissipation Without Derating
Board
Package
Θ
JA
Without Derating
(T
A
= 25°C)
(T
A
= 70°C)
High-K
RGW
30.5°C/W
3.27 W
1.8 W
TPS7A7X00EVM-
RGW
24°C/W
4 W
2.3 W
718
5
SLAU430 – February 2012
TPS7A7x00EVM-718 Evaluation Module
Copyright © 2012, Texas Instruments Incorporated