Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 数据表
产品代码
DK-TM4C129X
Register 6: GPTM Interrupt Mask (GPTMIMR), offset 0x018
This register allows software to enable/disable GPTM controller-level interrupts. Setting a bit enables
the corresponding interrupt, while clearing a bit disables it.
the corresponding interrupt, while clearing a bit disables it.
GPTM Interrupt Mask (GPTMIMR)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x018
Type RW, reset 0x0000.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x018
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
TATOIM
CAMIM
CAEIM
RTCIM
TAMIM
DMAAIM
reserved
TBTOIM
CBMIM
CBEIM
TBMIM
reserved
DMABIM
reserved
RW
RW
RW
RW
RW
RW
RO
RO
RW
RW
RW
RW
RO
RW
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000
RO
reserved
31:14
GPTM Timer B DMA Done Interrupt Mask
The
DMABIM
values are defined as follows:
Description
Value
Interrupt is disabled.
0
Interrupt is enabled.
1
0
RW
DMABIM
13
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
12
GPTM Timer B Match Interrupt Mask
The
TBMIM
values are defined as follows:
Description
Value
Interrupt is disabled.
0
Interrupt is enabled.
1
0
RW
TBMIM
11
GPTM Timer B Capture Mode Event Interrupt Mask
The
CBEIM
values are defined as follows:
Description
Value
Interrupt is disabled.
0
Interrupt is enabled.
1
0
RW
CBEIM
10
December 13, 2013
1140
Texas Instruments-Advance Information
General-Purpose Timers