Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 数据表
产品代码
DK-TM4C129X
Register 81: Floating-Point Context Control (FPCC), offset 0xF34
The FPCC register sets or returns FPU control data.
Floating-Point Context Control (FPCC)
Base 0xE000.E000
Offset 0xF34
Type RW, reset 0xC000.0000
Offset 0xF34
Type RW, reset 0xC000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
LSPEN
ASPEN
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LSPACT
USER
reserved
THREAD
HFRDY
MMRDY
BFRDY
reserved
MONRDY
reserved
RW
RW
RO
RW
RW
RW
RW
RO
RW
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Automatic State Preservation Enable
When set, enables the use of the
FRACTV
bit in the CONTROL register
on execution of a floating-point instruction. This results in automatic
hardware state preservation and restoration, for floating-point context,
on exception entry and exit.
hardware state preservation and restoration, for floating-point context,
on exception entry and exit.
Important:
Two bits control when
FPCA
can be enabled: the
ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the
register and the
DISFPCA
bit in the Auxiliary Control
(ACTLR) register.
1
RW
ASPEN
31
Lazy State Preservation Enable
When set, enables automatic lazy state preservation for floating-point
context.
context.
1
RW
LSPEN
30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
29:9
Monitor Ready
When set, DebugMonitor is enabled and priority permits setting
MON_PEND when the floating-point stack frame was allocated.
MON_PEND when the floating-point stack frame was allocated.
0
RW
MONRDY
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
7
Bus Fault Ready
When set, BusFault is enabled and priority permitted setting the BusFault
handler to the pending state when the floating-point stack frame was
allocated.
handler to the pending state when the floating-point stack frame was
allocated.
0
RW
BFRDY
6
Memory Management Fault Ready
When set, MemManage is enabled and priority permitted setting the
MemManage handler to the pending state when the floating-point stack
frame was allocated.
MemManage handler to the pending state when the floating-point stack
frame was allocated.
0
RW
MMRDY
5
213
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller