Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 数据表
产品代码
DK-TM4C129X
PLL Configuration
The PLL is disabled by default during power-on reset and is enabled later by software if required.
Software specifies the output divisor to set the system clock frequency and enables the PLL to drive
the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1 and PLLSTAT registers.
Changes made to these registers do not become active until after the
Software specifies the output divisor to set the system clock frequency and enables the PLL to drive
the output. The PLL is controlled using the PLLFREQ0, PLLFREQ1 and PLLSTAT registers.
Changes made to these registers do not become active until after the
NEWFREQ
bit in the RSCLKCFG
register is enabled.
The clock source for the main PLL is selected by configuring the
PLLSRC
field in the Run and Sleep
Clock Configuration (RSCLKCFG) register.
The PLL allows for the generation of system clock frequencies in excess of the reference clock
provided. The reference clocks for the PLL are the PIOSC and the MOSC. The PLL is controlled
by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (f
provided. The reference clocks for the PLL are the PIOSC and the MOSC. The PLL is controlled
by two registers, PLLFREQ0 and PLLFREQ1. The PLL VCO frequency (f
VCO
) is determined through
the following calculation:
f
VCO
= f
IN
* MDIV
where
f
IN
= f
XTAL
/(Q+1)(N+1) or f
PIOSC
/(Q+1)(N+1)
MDIV = MINT + (MFRAC / 1024)
The
Q
and
N
values are programmed in the PLLFREQ1 register. Note that to reduce jitter,
MFRAC
should be programmed to 0x0.
When the PLL is active, the system clock frequency (SysClk) is calculated using the following
equation:
equation:
SysClk = f
VCO
/ (PSYSDIV + 1)
The PLL system divisor factor (
PSYSDIV
) determines the value of the system clock. Table
5-6 on page 248 shows how the system divisor encodings affect the system clock frequency when
the f
the f
VCO
= 480 MHz.
Table 5-6. System Divisor Factors for f
vco
=480 MHz
f
VCO
(MHz)= 480 MHz
System Clock (SYSCLK) (MHz)
System Divisors (PSYSDIV +1)
a
4
120
8
60
10
48
16
30
20
24
40
12
80
6
a. The use of non-integer divisors introduce additional jitter which may affect interface performance.
If the main oscillator provides the clock reference to the PLL, the translation provided by hardware
and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers
(see page 303). The internal translation provides a translation within ± 1% of the targeted PLL VCO
frequency. Table 5-7 on page 249 shows the actual PLL frequency and error for a given crystal
choice.
and used to program the PLL is available for software in the PLL Frequency n (PLLFREQn) registers
(see page 303). The internal translation provides a translation within ± 1% of the targeted PLL VCO
frequency. Table 5-7 on page 249 shows the actual PLL frequency and error for a given crystal
choice.
December 13, 2013
248
Texas Instruments-Advance Information
System Control