Texas Instruments TPD4E05U06 Four Channel Ultra Low Capacitance IEC ESD Protection Diode Evaluation Module TPD4E05U06DQA TPD4E05U06DQAEVM 数据表
产品代码
TPD4E05U06DQAEVM
User's Guide
SLVU859 – February 2013
TPD4E05U06DQAEVM
The TPD4E05U06 is an ESD protection device with ultra low capacitance. This device is constructed with
a central ESD clamp with two hiding diodes to reduce the capacitive loading. It is rated to dissipate ESD
strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. Its ultra low
loading capacitance makes it ideal for protecting any high-speed signal pins.
a central ESD clamp with two hiding diodes to reduce the capacitive loading. It is rated to dissipate ESD
strikes above the maximum level specified in the IEC61000-4-2 level 4 international standard. Its ultra low
loading capacitance makes it ideal for protecting any high-speed signal pins.
1
Introduction
1.1
Features
•
Provides System Level ESD Protection for Low-Voltage IO Interfaces
•
IEC 61000-4-2 Level 4:
–
±12kV (Contact discharge)
–
±15kV (Air-gap discharge)
•
IO Capacitance 0.42pF (Typ)
•
DC Breakdown Voltage 6.5V (Min)
•
Ultra low Leakage Current 10nA (Max)
•
Low ESD Clamping Voltage
•
Industrial Temperature Range: –40°C to 125°C
•
Easy Straight-through Routing Package
1.2
Applications
•
HDMI control lines
•
USB3.0
•
MHL
•
LVDS
•
eSATA
•
DisplayPort
•
PCI Express
2
EVM Description and Configuration
The TPD4E05U06DQAEVM is designed to allow 4-port analysis through a 100
Ω
TMDS line, or differential
pair. The board material is Rogers Board RO4350 with a Dielectric Constant,
ε
r, of 3.48 +/- 0.05 and a
loss tangent,
δ
, of 0.0031 at 2.5 GHz. The port connectors are surface-mount SMP 50
Ω
high speed
connectors.
The EVM has two sections: CALIBRATION and TPD4E05U06DQA. The traces on the CALIBRATION
section are identical to the traces on the TPD4E05U06DQA section, allowing the board’s effect to be
removed and only the device under test’s performance to be evaluated, without having to de-solder the
device under test.
section are identical to the traces on the TPD4E05U06DQA section, allowing the board’s effect to be
removed and only the device under test’s performance to be evaluated, without having to de-solder the
device under test.
1
SLVU859 – February 2013
TPD4E05U06DQAEVM
Copyright © 2013, Texas Instruments Incorporated