Texas Instruments DS100BR111EVK Evaluation Module DS100BR111EVK/NOPB DS100BR111EVK/NOPB 数据表
产品代码
DS100BR111EVK/NOPB
SNLS338E – JANUARY 2011 – REVISED FEBRUARY 2013
NOTE
Settings are approximate and will change based on PCB material, trace dimensions, and
driver waveform characteristics.
driver waveform characteristics.
Table 3. De-emphasis and Output Voltage Settings
Level
VOD_SEL
DEMA/B
SMBus Register DEM Level
SMBus Register VOD Level
VOD (mV)
DEM (dB)
1
0
0
000
000
700
0
2
0
Float
010
000
700
- 3.5
3
0
R
011
000
700
- 6
4
0
1
101
000
700
- 9
5
Float
0
000
011
1000
0
6
Float
Float
010
011
1000
- 3.5
7
Float
R
011
011
1000
- 6
8
Float
1
101
011
1000
- 9
9
R
0
000
101
1200
- 0
10
R
Float
010
101
1200
- 3.5
11
R
R
011
101
1200
- 6
12
R
1
101
101
1200
- 9
13
1
0
000
100
1100
0
14
1
Float
001
100
1100
- 1.5
15
1
R
001
110
1300
- 1.5
16
1
1
010
110
1300
- 3.5
NOTE
The DS100BR111 VOD for OUTPUT A is limited to 700 mV in pin mode (ENSMB=0). With
ENSMB = 1 or FLOAT, the VOD for OUTPUT A can be adjusted with SMBus register
0x23 [4:2] as shown in
ENSMB = 1 or FLOAT, the VOD for OUTPUT A can be adjusted with SMBus register
0x23 [4:2] as shown in
.
NOTE
When VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the DS100BR111 will
support 10G-KR back-channel communication using pin control.
support 10G-KR back-channel communication using pin control.
NOTE
In SMBus Mode if VOD_SEL is in the Logic 1 state (1K resistor to VIN/VDD) the
DS100BR111 AD0-AD3 pins are internally forced to 0'h
DS100BR111 AD0-AD3 pins are internally forced to 0'h
Table 4. Signal Detect Threshold Level
SMBus REG bit
SD_TH
Assert Level (Typical)
De-assert Level (Typical)
[3:2] and [1:0]
0
10
210 mV
150 mV
20K to GND
01
160 mV
100 mV
Float (Default)
00
180 mV
110 mV
1
11
190 mV
130 mV
Note: VDD = 2.5V, 25°C, and 010101 pattern at 10 Gbps
Copyright © 2011–2013, Texas Instruments Incorporated
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