Texas Instruments 4.5V to 18V Input, 3A SWIFT Converter Evaluation Module TPS54326EVM-540 TPS54326EVM-540 数据表
产品代码
TPS54326EVM-540
500
600
700
800
900
0
5
10
15
20
V - Input Voltage - V
I
f
-SwitchingFrequency-kHz
sw
V
= 1.8 V
O
V
= 3.3 V
O
I
= 1 A
O
Board Layout
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2.10 Switching Frequency
The TPS54326EVM-540 switching frequency is shown in
Figure 8. TPS54326-540 Switching Frequency
3
Board Layout
This section provides description of the TPS54326EVM-540, board layout, and layer illustrations.
3.1
Layout
The board layout for the TPS54326EVM-540 and is shown in
through
. The top layer
contains the main power traces for VIN, VO and ground. Also on the top layer are connections for the pins
of the TPS54326 and a large area filled with ground. Many of the signal traces are also located on the top
side. The input decoupling capacitor are located as close to the IC as possible. The input and output
connectors, test points and most of the components are located on the top side. R3, the 0-
of the TPS54326 and a large area filled with ground. Many of the signal traces are also located on the top
side. The input decoupling capacitor are located as close to the IC as possible. The input and output
connectors, test points and most of the components are located on the top side. R3, the 0-
Ω
resistor that
connects VIN to VCC and R4, the power good pull up, are located on the back side. Analog ground and
power ground are connected at a single point on the top layer near pin 5 of the TPS54326. The internal
layer 1 is a split plane containing analog and power grounds. The internal layer 2 is primarily power
ground. There are also a fill area of VIN and a trace routing VCC to the enable control jumper JP1. The
bottom layer is primarily analog ground. There are also traces to connect VIN to VCC through R3, traces
for the power good signal and the feedback trace from VOUT to the voltage setpoint divider network.
power ground are connected at a single point on the top layer near pin 5 of the TPS54326. The internal
layer 1 is a split plane containing analog and power grounds. The internal layer 2 is primarily power
ground. There are also a fill area of VIN and a trace routing VCC to the enable control jumper JP1. The
bottom layer is primarily analog ground. There are also traces to connect VIN to VCC through R3, traces
for the power good signal and the feedback trace from VOUT to the voltage setpoint divider network.
8
SLVU353 – November 2009
TPS54326EVM-540 3-A, SWIFT
TM
Regulator Evaluation Module
Copyright © 2009, Texas Instruments Incorporated