Texas Instruments AM18x evaluation module with Wi-Fi TMDXEVMWIFI1808L TMDXEVMWIFI1808L 数据表
产品代码
TMDXEVMWIFI1808L
SPRS653E – FEBRUARY 2010 – REVISED MARCH 2014
6.24 LCD Controller (LCDC)
The LCD controller consists of two independent controllers, the Raster Controller and the LCD Interface
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
Display Driver (LIDD) controller. Each controller operates independently from the other and only one of
them is active at any given time.
•
The Raster Controller handles the synchronous LCD interface. It provides timing and data for constant
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
graphics refresh to a passive display. It supports a wide variety of monochrome and full-color display
types and sizes by use of programmable timing controls, a built-in palette, and a gray-scale/serializer.
Graphics data is processed and stored in frame buffers. A frame buffer is a contiguous memory block
in the system. A built-in DMA engine supplies the graphics data to the Raster engine which, in turn,
outputs to the external LCD device.
•
The LIDD Controller supports the asynchronous LCD interface. It provides full-timing programmability
of control signals (CS, WE, OE, ALE) and output data.
of control signals (CS, WE, OE, ALE) and output data.
The maximum resolution for the LCD controller is 1024 x 1024 pixels. The maximum frame rate is
determined by the image size in combination with the pixel clock rate. For details, see
determined by the image size in combination with the pixel clock rate. For details, see
lists the LCD Controller registers.
Table 6-103. LCD Controller Registers
BYTE ADDRESS
ACRONYM
REGISTER DESCRIPTION
0x01E1 3000
REVID
LCD Revision Identification Register
0x01E1 3004
LCD_CTRL
LCD Control Register
0x01E1 3008
LCD_STAT
LCD Status Register
0x01E1 300C
LIDD_CTRL
LCD LIDD Control Register
0x01E1 3010
LIDD_CS0_CONF
LCD LIDD CS0 Configuration Register
0x01E1 3014
LIDD_CS0_ADDR
LCD LIDD CS0 Address Read/Write Register
0x01E1 3018
LIDD_CS0_DATA
LCD LIDD CS0 Data Read/Write Register
0x01E1 301C
LIDD_CS1_CONF
LCD LIDD CS1 Configuration Register
0x01E1 3020
LIDD_CS1_ADDR
LCD LIDD CS1 Address Read/Write Register
0x01E1 3024
LIDD_CS1_DATA
LCD LIDD CS1 Data Read/Write Register
0x01E1 3028
RASTER_CTRL
LCD Raster Control Register
0x01E1 302C
RASTER_TIMING_0
LCD Raster Timing 0 Register
0x01E1 3030
RASTER_TIMING_1
LCD Raster Timing 1 Register
0x01E1 3034
RASTER_TIMING_2
LCD Raster Timing 2 Register
0x01E1 3038
RASTER_SUBPANEL
LCD Raster Subpanel Display Register
0x01E1 3040
LCDDMA_CTRL
LCD DMA Control Register
0x01E1 3044
LCDDMA_FB0_BASE
LCD DMA Frame Buffer 0 Base Address Register
0x01E1 3048
LCDDMA_FB0_CEILING
LCD DMA Frame Buffer 0 Ceiling Address Register
0x01E1 304C
LCDDMA_FB1_BASE
LCD DMA Frame Buffer 1 Base Address Register
0x01E1 3050
LCDDMA_FB1_CEILING
LCD DMA Frame Buffer 1 Ceiling Address Register
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Peripheral Information and Electrical Specifications
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