Microchip Technology DM300023 数据表
dsPIC30F1010/202X
DS80290J-page 10
© 2008 Microchip Technology Inc.
17. Module: SPI Module
The SMP bit (SPIxCON1<9>, where x = 1 or 2)
does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master
mode. In this mode, whether the SMP bit is set or
cleared, the data is always sampled at the end of
data output time.
does not have any effect when the SPI module is
configured for a 1:1 prescale factor in Master
mode. In this mode, whether the SMP bit is set or
cleared, the data is always sampled at the end of
data output time.
Work around
If sampling at the middle of data output time is
required, then configure the SPI module to use a
clock prescale factor other than 1:1 using the
PPRE<1:0> and SPRE<2:0> bits in the
SPIxCON1 register.
required, then configure the SPI module to use a
clock prescale factor other than 1:1 using the
PPRE<1:0> and SPRE<2:0> bits in the
SPIxCON1 register.
18. Module: I
2
C Module
The Bus Collision Status bit (BCL) does not get set
when a bus collision occurs during a Restart or
Stop event. However, the BCL bit gets set when a
bus collision occurs during a Start event.
when a bus collision occurs during a Restart or
Stop event. However, the BCL bit gets set when a
bus collision occurs during a Start event.
Work around
None.
Note:
The dsPIC30F1010/202X devices have
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.
only one SPI. All references to x = 2 are
intended for software compatibility with
other dsPIC DSC devices.