Microchip Technology MCP4728EV 数据表
MCP4728
DS22187E-page 34
© 2010 Microchip Technology Inc.
5.5
Writing and Reading Registers
and EEPROM
and EEPROM
The Master (MCU) can write or read the DAC input
registers or EEPROM using the I
registers or EEPROM using the I
2
C interface
command.
The following sections describe the communication
examples to write and read the DAC registers and
EEPROM using the I
examples to write and read the DAC registers and
EEPROM using the I
2
C interface.
5.6
Write Commands for DAC
Registers and EEPROM
Registers and EEPROM
summarizes the write command types and
their functions.The write command is defined by using
three write command type bits (C
three write command type bits (C
2
, C
1
, C
0
) and two
write function bits (W1, W0). The register selection bits
(DAC1, DAC0) are used to select the DAC channel.
(DAC1, DAC0) are used to select the DAC channel.
TABLE 5-1:
WRITE COMMAND TYPES
Command Field
Write
Function
Command Name
Function
C2
C1
C0
W1
W0
Fast Mode Write
0
0
X
Not Used
Fast Write for DAC
Input Registers
This command writes to the DAC input registers sequentially with
limited configuration bits. The data is sent sequentially from channels A
to D. The input register is written at the acknowledge clock pulse of the
channel’s last input data byte. EEPROM is not affected.
limited configuration bits. The data is sent sequentially from channels A
to D. The input register is written at the acknowledge clock pulse of the
channel’s last input data byte. EEPROM is not affected.
)
Write DAC Input Register and EEPROM
0
1
0
0
0
Multi-Write for DAC
Input Registers
This command writes to multiple DAC input registers, one DAC input
register at a time. The writing channel register is defined by the DAC
selection bits (DAC1, DAC0). EEPROM is not affected.
register at a time. The writing channel register is defined by the DAC
selection bits (DAC1, DAC0). EEPROM is not affected.
(
1
0
Sequential Write for
DAC Input Registers
and EEPROM
DAC Input Registers
and EEPROM
This command writes to both the DAC input registers and EEPROM
sequentially. The sequential writing is carried out from a starting
channel to channel D. The starting channel is defined by the DAC
selection bits (DAC1 and DAC0).
The input register is written at the acknowledge clock pulse of the last
input data byte of each register. However, the EEPROM data is written
altogether at the same time sequentially at the end of the last byte.
sequentially. The sequential writing is carried out from a starting
channel to channel D. The starting channel is defined by the DAC
selection bits (DAC1 and DAC0).
The input register is written at the acknowledge clock pulse of the last
input data byte of each register. However, the EEPROM data is written
altogether at the same time sequentially at the end of the last byte.
(
),(
1
1
Single Write for DAC
Input Register and
EEPROM
This command writes to a single selected DAC input register and its
EEPROM. Both the input register and EEPROM are written at the
acknowledge clock pulse of the last input data byte. The writing
channel is defined by the DAC selection bits (DAC1 and DAC0)
EEPROM. Both the input register and EEPROM are written at the
acknowledge clock pulse of the last input data byte. The writing
channel is defined by the DAC selection bits (DAC1 and DAC0)
.
(
),(
Write I
2
C Address Bits (A2, A1, A0)
0
1
1
Not Used
Write I
2
C Address Bits This command writes new I
2
C address bits (A2, A1, A0) to the DAC
input register and EEPROM.
Write V
REF
, Gain, and Power-Down Select Bits (
)
1
0
0
Not Used
Write Reference
(V
REF
) selection bits
to Input Registers
This command writes Reference (V
REF
) selection bits of each channel.
1
1
0
Not Used
Write Gain selection
bits to Input Registers
This command writes Gain selection bits of each channel.
1
0
1
Not Used
Write Power-Down
bits to Input Registers
This command writes Power-Down bits of each channel.
Note 1:
The analog output is updated when LDAC pin is (or changes to) “Low”. UDAC bit is not used for this command.
2:
The DAC output is updated when LDAC pin or UDAC bit is “Low”.
3:
The device starts writing to the EEPROM on the acknowledge clock pulse of the last channel. The device does not
execute any command until RDY/BSY bit comes back to “High”.
execute any command until RDY/BSY bit comes back to “High”.
4:
The input and output registers are updated at the acknowledge clock pulse of the last byte. The update does not require
LDAC pin or UDAC bit conditions. EEPROM is not affected.
LDAC pin or UDAC bit conditions. EEPROM is not affected.