Microchip Technology SST39LF400A-55-4C-EKE Memory IC TSOP-48 SST39LF400A-55-4C-EKE 数据表
产品代码
SST39LF400A-55-4C-EKE
© 2011 Silicon Storage Technology, Inc.
DS25001A
03/11
8
2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash
SST39LF200A / SST39LF400A / SST39LF800A
SST39VF200A / SST39VF400A / SST39VF800A
Data Sheet
A Microchip Technology Company
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing dia-
gram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 10 for timing dia-
gram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored.
Write Operation Status Detection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide two software means to detect
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ
the completion of a write (Program or Erase) cycle, in order to optimize the system write cycle time.
The software detection includes two status bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-
Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or
Erase operation.
Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
are valid, then the device has completed the write cycle, otherwise the rejection is valid.
Data# Polling (DQ
7
)
When the SST39LF200A/400A/800A and SST39VF200A/400A/800A are in the internal Program oper-
ation, any attempt to read DQ
ation, any attempt to read DQ
7
will produce the complement of the true data. Once the Program oper-
ation is completed, DQ
7
will produce true data. Note that even though DQ
7
may have valid data
immediately following the completion of an internal Write operation, the remaining data outputs may
still be invalid: valid data on the entire data bus will appear in subsequent successive Read
still be invalid: valid data on the entire data bus will appear in subsequent successive Read
cycles after
an interval of 1 µs
. During internal Erase operation, any attempt to read DQ
7
will produce a ‘0’. Once
the internal Erase operation is completed, DQ
7
will produce a ‘1’. The Data# Polling is valid after the
rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling
timing diagram and Figure 19 for a flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is
completed, the DQ
completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. The Toggle
Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-
or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for
Toggle Bit timing diagram and Figure 19 for a flowchart.
Data Protection
The SST39LF200A/400A/800A and SST39VF200A/400A/800A provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
features to protect nonvolatile data from inadvertent writes.